Sangyeop Baeck
Orcid: 0000-0002-9106-5461
According to our database1,
Sangyeop Baeck
authored at least 8 papers
between 2019 and 2024.
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Bibliography
2024
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology.
IEEE J. Solid State Circuits, April, 2024
2023
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2019
A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019