Chen Yang

According to our database, Chen Yang authored at least 48 papers between 2014 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow.

Yishuo Meng, Jianfei Wang, Qiang Fu, Jia Hou, Siwei Xiang, Ge Li, Chen Yang

IEEE Trans. Very Large Scale Integr. Syst., September, 2025

Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme.

Yishuo Meng, Jianfei Wang, Siwei Xiang, Jia Hou, Zhijie Lin, Kuizhi Mei, Chen Yang

IEEE Trans. Circuits Syst. I Regul. Pap., August, 2025

A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline.

Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang

IEEE Trans. Very Large Scale Integr. Syst., May, 2025

A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme.

Jianfei Wang, Chen Yang, Yishuo Meng, Fahong Zhang, Jia Hou, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2025

A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering.

Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method.

Yishuo Meng, Junfeng Wu, Siwei Xiang, Jianfei Wang, Jia Hou, Zhijie Lin, Chen Yang

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption.

Jianfei Wang, Chen Yang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Leibo Liu

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm.

Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data.

Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography.

Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, December, 2024

A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination.

Wenzheng He, Zikuo Lu, Xin Liu, Ziwei Xu, Jingshuo Zhang, Chen Yang, Li Geng

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

A Novel Two-Level Protection Scheme against Hardware Trojans on a Reconfigurable CNN Accelerator.

Zichu Liu, Jia Hou, Jianfei Wang, Chen Yang

Cryptogr., September, 2024

ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach.

Yishuo Meng, Siwei Xiang, Jianfei Wang, Jia Hou, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.

Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units.

Chen Yang, Yaoyao Yang, Yishuo Meng, Kaibo Huo, Siwei Xiang, Jianfei Wang, Li Geng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks.

Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei

IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.

Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm.

Fahong Zhang, Chen Yang, Rui Zong, Xinran Zheng, Jianfei Wang, Yishuo Meng

IEEE Trans. Inf. Forensics Secur., 2024

LSTM-CRP: Algorithm-Hardware Co-Design and Implementation of Cache Replacement Policy Using Long Short-Term Memory.

Yizhou Wang, Yishuo Meng, Jiaxing Wang, Chen Yang

Big Data Cogn. Comput., 2024

2023

A Real-Time and Efficient Optical Flow Tracking Accelerator on FPGA Platform.

Yifan Gong, Jinshuo Zhang, Xin Liu, Jialin Li, Ying Lei, Zhe Zhang, Chen Yang, Li Geng

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access.

Chen Yang, Junfeng Wu, Siwei Xiang, Liyan Liang, Li Geng

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow.

Yishuo Meng, Chen Yang, Siwei Xiang, Jianfei Wang, Kuizhi Mei, Li Geng

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm.

Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Yang Su

IEEE Trans. Very Large Scale Integr. Syst., August, 2023

DRGN: a dynamically reconfigurable accelerator for graph neural networks.

Chen Yang, Kaibo Huo, Long-Fei Geng, Kuizhi Mei

J. Ambient Intell. Humaniz. Comput., July, 2023

POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection.

Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang

Inf., 2023

An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method.

Yuheng Xia, Yishuo Meng, Siwei Xiang, Jianfei Wang, Chen Yang

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2022

A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers.

Chen Yang, Yishuo Meng, Kaibo Huo, Jiawei Xi, Kuizhi Mei

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication.

Yang Su, Bai-Long Yang, Chen Yang, Zepeng Yang, Yi-Wei Liu

IEEE Trans. Very Large Scale Integr. Syst., 2022

ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation.

Yang Su, Bai-Long Yang, Chen Yang, Songyin Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks.

Chen Yang, Jia Hou, Yizhou Wang, Haibo Zhang, Xiaoli Wang, Li Geng

J. Circuits Syst. Comput., 2022

SDF-SLAM: A Deep Learning Based Highly Accurate SLAM Using Monocular Camera Aiming at Indoor Map Reconstruction With Semantic and Depth Fusion.

Chen Yang, Qi Chen, Yaoyao Yang, Jingyu Zhang, Minshun Wu, Kuizhi Mei

IEEE Access, 2022

A Hardware Architecture of Feature Extraction for Real-Time Visual SLAM.

Jialin Li, Liangji Zhang, Xuewei Shen, Yifan Gong, Ying Lei, Chen Yang, Li Geng

Proceedings of the IECON 2022, 2022

2021

UL-CNN: An Ultra-Lightweight Convolutional Neural Network Aiming at Flash-Based Computing-In-Memory Architecture for Pedestrian Recognition.

Chen Yang, Jingyu Zhang, Qi Chen, Yi Xu, Cimang Lu

J. Circuits Syst. Comput., 2021

High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor.

Yang Su, Bai-Long Yang, Chen Yang, Jing-Yuan He

J. Ambient Intell. Humaniz. Comput., 2021

A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference.

Chen Yang, Zepeng Yang, Jia Hou, Yang Su

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

A Stride-Based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware Implementation.

Chen Yang, Yizhou Wang, Xiaoli Wang, Li Geng

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

FPGA-Based Hardware Accelerator for Leveled Ring-LWE Fully Homomorphic Encryption.

Yang Su, Bailong Yang, Chen Yang, Luogeng Tian

IEEE Access, 2020

CRP: Context-directed Replacement Policy to Improve Cache Performance for Coarse-Grained Reconfigurable Arrays.

Chen Yang, Jia Hou, Yizhou Wang, Li Geng

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks.

Chen Yang, Yizhou Wang, Xiaoli Wang, Li Geng

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Fully Quantitative Scheme With Fine-grained Tuning Method For Lightweight CNN Acceleration.

Chen Yang, Bowen Li, Yizhou Wang

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

CCP: Configuration Context based Prefetching to Improve Coarse-Grained Reconfigurable Array Performance.

Chen Yang, Jia Hou, Yizhou Wang, Qi Zhou, Li Geng

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing.

Leibo Liu, Zhaoshi Li, Chen Yang, Chenchen Deng, Shouyi Yin, Shaojun Wei

IEEE Trans. Circuits Syst. II Express Briefs, 2018

CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance.

Leibo Liu, Chen Yang, Shouyi Yin, Shaojun Wei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays.

Chen Yang, Leibo Liu, Kai Luo, Shouyi Yin, Shaojun Wei

IEEE Trans. Parallel Distributed Syst., 2017

2016

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays.

Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array.

Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei

J. Circuits Syst. Comput., 2015

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only).

Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014

Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor.

Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014