Chenhan Wei
Orcid: 0000-0003-2683-9835
According to our database1,
Chenhan Wei
authored at least 5 papers
between 2023 and 2025.
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Bibliography
2025
A 28nm 3.14 TFLOP/W BF16 LLM Fine-Tuning Processor with Asymmetric Quantization Computing for AI PC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
MPICC: Multiple-Precision Inter-Combined MAC Unit with Stochastic Rounding for Ultra-Low-Precision Training.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis.
IEEE J. Solid State Circuits, September, 2024
2023
A 28nm 1.07TFLOPS/mm<sup>2</sup> Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023