Ruoyang Liu

Orcid: 0000-0001-9873-6574

According to our database1, Ruoyang Liu authored at least 13 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Entropy Solutions to the Dirichlet Problem for Nonlinear Diffusion Equations with Conservative Noise.
SIAM J. Math. Anal., February, 2024

2023
Screening Image Features of Collapsed Buildings for Operational and Rapid Remote Sensing Identification.
Remote. Sens., December, 2023

A 28nm 1.07TFLOPS/mm<sup>2</sup> Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications.
IEEE J. Solid State Circuits, 2022

Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration.
IEEE J. Solid State Circuits, 2021

PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm<sup>2</sup>and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019


  Loading...