Yixiong Yang

Orcid: 0000-0002-3035-709X

According to our database1, Yixiong Yang authored at least 19 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 1.07TFLOPS/mm<sup>2</sup> Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

A Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications.
IEEE J. Solid State Circuits, 2022

Image Editing of Light and Color from a Single Image: A Baseline Framework.
Proceedings of the 30th Color and Imaging Conference, 2022

Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2020
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

2019
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
IEEE J. Solid State Circuits, 2019

Impact of supply chain information sharing on performance of fashion enterprises.
J. Enterp. Inf. Manag., 2019

A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2015
The mechanism of China textile industry shift: Strategies and behaviors of buyers and suppliers.
Proceedings of the 2015 IEEE International Conference on Industrial Engineering and Engineering Management, 2015


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