Jinshan Yue

According to our database1, Jinshan Yue authored at least 16 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning.
CoRR, 2020

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm<sup>2</sup>and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Accelerating CNN-RNN Based Machine Health Monitoring on FPGA.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead.
Proceedings of the 53rd Annual Design Automation Conference, 2016