Chennian Di

According to our database, Chennian Di authored at least 8 papers between 1992 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Adapting an industrial memory BIST solution for testing CAMs.

Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim

Proceedings of the International Test Conference in Asia, 2017

1996

An efficient CMOS bridging fault simulator: with SPICE accuracy.

Chennian Di, Jochen A. G. Jess

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1994

Probability Analysis for CMOS Floating Gate Faults.

Hua Xue, Chennian Di, Jochen A. G. Jess

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

On CMOS bridge fault modeling and test pattern evaluation.

Chennian Di, Jochen A. G. Jess

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

On Accurate Modeling and Efficient Simulation of CMOS Opens.

Chennian Di, Jochen A. G. Jess

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

A net-oriented method for realistic fault analysis.

Hua Xue, Chennian Di, Jochen A. G. Jess

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Fast Multi-Layer Critical Area Computation.

Hua Xue, Chennian Di, Jochen A. G. Jess

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

IC defect sensitivity for footprint-type spot defects.

José Pineda de Gyvez, Chennian Di

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992