Jais Abraham

According to our database1, Jais Abraham authored at least 9 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2022
Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test.
Proceedings of the IEEE International Test Conference, 2022

2017
Adapting an industrial memory BIST solution for testing CAMs.
Proceedings of the International Test Conference in Asia, 2017

2016
Test Time Minimisation in Scan Compression Designs Using Dynamic Channel Allocation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2008
Evaluation of Entropy Driven Compression Bounds on Industrial Designs.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Multi-Cycle Sensitizable Transition Delay Faults.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2002
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000
A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000


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