José Pineda de Gyvez

According to our database1, José Pineda de Gyvez authored at least 109 papers between 1989 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions defect oriented testing of integrated circuits".

Timeline

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Bibliography

2019
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention.
IEEE Trans. VLSI Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

Enhancing sensitivity-based power reduction for an industry IC design context.
Integration, 2019

Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs.
Integration, 2019

Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Chip Health Tracking Using Dynamic In-Situ Delay Monitoring.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units.
IEEE Trans. Computers, 2018

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Low power latch based design with smart retiming.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Logic Design Partitioning for Stacked Power Domains.
IEEE Trans. VLSI Syst., 2017

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling.
J. Solid-State Circuits, 2017

Reconfigurable Support Vector Machine Classifier with Approximate Computing.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

An analytical model for interdependent setup/hold-time characterization of flip-flops.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A scan-chain based state retention methodology for IoT processors operating on intermittent energy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Floorplan and placement methodology for improved energy reduction in stacked power-domain design.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A microcontroller with 96% power-conversion efficiency using stacked voltage domains.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Circuit valorization in the IC design ecosystem.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Lower power by voltage stacking: a fine-grained system design approach.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
An Improved Methodology for Resilient Design Implementation.
ACM Trans. Design Autom. Electr. Syst., 2015

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Supervised learning based model for predicting variability-induced timing errors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Digital Systems Power Management for High Performance Mixed Signal Platforms.
IEEE Trans. on Circuits and Systems, 2014

Sub-threshold custom standard cell library validation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Standard cell library tuning for variability tolerant designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Architectural Analysis for Wirelessly Powered Computing Platforms.
IEEE Trans. VLSI Syst., 2013

Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking.
IEEE Trans. Computers, 2013

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

2012
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits.
IEEE Trans. VLSI Syst., 2012

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS.
IEEE Trans. Instrumentation and Measurement, 2012

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters.
J. Low Power Electronics, 2012

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.
Proceedings of the IEEE 25th International SOC Conference, 2012

Sliding-Mode Control to Compensate PVT Variations in dual core systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Standard cell sizing for subthreshold operation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs.
IEEE Trans. on Circuits and Systems, 2011

A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage.
J. Solid-State Circuits, 2010

Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation.
J. Low Power Electronics, 2010

Body bias driven design synthesis for optimum performance per area.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A forward body bias generator for digital CMOS circuits with supply voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Analog Automatic Test Pattern Generation for Quasi-Static Structural Test.
IEEE Trans. VLSI Syst., 2009

An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

An energy-aware multiplier based on a Configurable-Reuse of points design methodology.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Calibration and Debugging of Multi-step Analog to Digital Converters.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters.
Proceedings of the Design, Automation and Test in Europe, 2008

Statistical noise margin estimation for sub-threshold combinational circuits.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Efficient testing and diagnosis of faulty power switches in SOCs.
IET Computers & Digital Techniques, 2007

Vt balancing and device sizing towards high yield of sub-threshold static logic gates.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.
J. Low Power Electronics, 2006

Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.
J. Electronic Testing, 2006

Testing and Diagnosis of Power Switches in SOCs.
Proceedings of the 11th European Test Symposium, 2006

2005
A capacitor cross-coupled common-gate low-noise amplifier.
IEEE Trans. on Circuits and Systems, 2005

Multi-VDD Testing for Analog Circuits.
J. Electronic Testing, 2005

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.
Proceedings of the Integrated Circuit and System Design, 2005

Power-scan chain: design for analog testability.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Functional vs. multi-VDD testing of RF circuits.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Word line pulsing technique for stability fault detection in SRAM cells.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

On-chip digital power supply control for system-on-chip applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Glitch-free discretely programmable clock generation on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Limits to performance spread tuning using adaptive voltage and body biasing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Evaluation of signature-based testing of RF/analog circuits.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Programmable techniques for cell stability test and debug in embedded SRAMs.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Low Energy Switch Block For FPGAs.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Power Supply Ramping for Quasi-static Testing of PLLs.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Technology exploration for adaptive power and frequency scaling in 90nm CMOS.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Low energy FPGA interconnect design.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Power Supply Noise Monitor for Signal Integrity Faults.
Proceedings of the 2004 Design, 2004

2003
Prelayout interconnect yield prediction.
IEEE Trans. VLSI Syst., 2003

Threshold Voltage Mismatch (DeltaVT) Fault Modeling.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

An Analog Integrated Circuit Design Laboratory.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

VDD Ramp Testing for RF Circuits.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Encoded-Low Swing Technique for Ultra Low Power Interconnect.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Resistance Characterization for Weak Open Defects.
IEEE Design & Test of Computers, 2002

2001
Average Leakage Current Estimation of CMOS Logic Circuits.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Yield modeling and BEOL fundamentals.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Pre-layout prediction of interconnect manufacturability.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

2000
Full-signature real-time corrosion detection of underground casing pipes.
IEEE Trans. Instrumentation and Measurement, 2000

Nonlinear Computability Based on Chaos.
I. J. Bifurcation and Chaos, 2000

Real-time wavelet-integrated corrosion detection system for casing pipes.
Integrated Computer-Aided Engineering, 2000

Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Subband coding and image compression using CNN.
I. J. Circuit Theory and Applications, 1999

CMOS cryptosystem using a Lorenz chaotic oscillator.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Chaotic generation of PN sequences: a VLSI implementation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Time multiplexed color image processing based on a CNN with cell-state outputs.
IEEE Trans. VLSI Syst., 1998

1996
Color image processing in a cellular neural-network environment.
IEEE Trans. Neural Networks, 1996

Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing.
Real-Time Imaging, 1996

Preprocessing operators for image compression using cellular neural networks.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995
Time Domain Analog Wavelet Transform in Real-Time.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Universal Interface Between PC and Neural Networks Hardware.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
A power supply ramping and current measurement based technique for analog fault diagnosis.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Behavioral Testing of Cellular Neural Networks.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Time-Mulitplexing CNN Simulator.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Single-Layer CNN Simulator.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Integrated circuit defect-sensitivity - theory and computational models.
The Kluwer international series in engineering and computer science 208, Kluwer, ISBN: 978-0-7923-9306-1, 1993

1992
IC defect sensitivity for footprint-type spot defects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

1989
On the design and implementation of a wafer yield editor.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

A layout defect-sensitivity extractor.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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