Benoit Nadeau-Dostie

According to our database1, Benoit Nadeau-Dostie authored at least 28 papers between 1989 and 2020.

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Bibliography

2020
MBIST Supported Multi Step Trim for Reliable eMRAM Sensing.
Proceedings of the IEEE International Test Conference, 2020

Memory repair logic sharing techniques and their impact on yield.
Proceedings of the IEEE International Test Conference, 2020

MBIST Support for Reliable eMRAM Sensing.
Proceedings of the IEEE European Test Symposium, 2020

2018
Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions.
Proceedings of the IEEE International Test Conference in Asia, 2018

2017
Adapting an industrial memory BIST solution for testing CAMs.
Proceedings of the International Test Conference in Asia, 2017

2015
Low-Power Programmable PRPG With Test Compression Capabilities.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
Timing-Aware ATPG.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014

2012
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops.
IEEE Trans. Computers, 2012

Test generator with preselected toggling for low power built-in self-test.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011
Power Aware Embedded Test.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2009
Improved Core Isolation and Access for Hierarchical Embedded Test.
IEEE Des. Test Comput., 2009

Test point insertion using functional flip-flops to drive control points.
Proceedings of the 2009 IEEE International Test Conference, 2009

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks.
Proceedings of the 2008 IEEE International Test Conference, 2008

2006
OCI: Open Compression Interface.
Proceedings of the 2006 IEEE International Test Conference, 2006

2004
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

2002
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An embedded technique for at-speed interconnect testing.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1996
Built-In Self-Test: Assuring System Integrity.
Computer, 1996

1995
A New Hardware Fault Insertion Scheme for System Diagnostics Verification.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
ScanBist: A Multifrequency Scan-Based BIST Method.
IEEE Des. Test Comput., 1994

1992
BIST of PCB interconnects using boundary-scan architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Scan testing of latch arrays.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

ScanBIST: A Multi-frequency Scan-based BIST Method.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1990
Serial Interfacing for Embedded-Memory Testing.
IEEE Des. Test Comput., 1990

A new procedure for weighted random built-in self-test.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
Testing of Glue Logic Interconnects Using Boundary Scan Architecture.
Proceedings of the Proceedings International Test Conference 1989, 1989


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