Chi-Chang Lu

According to our database1, Chi-Chang Lu authored at least 22 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme.
IEEE Access, 2020

A High-Precision Bandgap Reference With a V-Curve Correction Circuit.
IEEE Access, 2020

2019
1.2 V 10-bits 40 MS/s CMOS SAR ADC for low-power applications.
IET Circuits Devices Syst., 2019

Capacitive digital-to-analog converter for low-power SAR ADCs.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2015
A Study of the Accessible Approach to Replace the Reservoir Silt Glaze with New Formula.
Proceedings of the Cross-Cultural Design Methods, Practice and Impact, 2015

2014
Cultural Creativity in Design Strategy: A Case Study of User's Preference of a Bird-Shaped Teapot.
Proceedings of the Cross-Cultural Design, 2014

2013
A 1.2V 10-bit 5 MS/s CMOS cyclic ADC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Research on Symbol Expression for Eye Image in Product Design: The Usage of the Chinese Traditional "Yun Wen".
Proceedings of the Cross-Cultural Design. Methods, Practice, and Case Studies, 2013

2011
A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit.
Circuits Syst. Signal Process., 2011

A Study of Producing Ceramic Glaze Utilizing Shihmen Reservoir Silt.
Proceedings of the Internationalization, Design and Global Development, 2011

Design for Aesthetic Experience.
Proceedings of the Internationalization, Design and Global Development, 2011

2010
Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers.
Circuits Syst. Signal Process., 2010

A 1.5V 12-b 40 MSamples/s CMOS pipelined ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2008
A CMOS low-voltage fully differential sample-and-hold circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuit.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
A fully differential low-voltage CMOS high-speed track-and-hold circuit.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A low-voltage fully differential CMOS high-speed track-and-hold circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002


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