Chien-Chun Tsai
According to our database1,
Chien-Chun Tsai
authored at least 10 papers
between 2002 and 2022.
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On csauthors.net:
Bibliography
2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE J. Solid State Circuits, 2020
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 7nm 4GHz Arm<sup>®</sup>-core-based CoWoS<sup>®</sup> Chiplet Design for High Performance Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2016
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
2014
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.
IEEE J. Solid State Circuits, 2014
2010
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2002
High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002