Wen-Hung Huang

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.


A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.
IEEE J. Solid State Circuits, 2020

A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 7nm 4GHz Arm<sup>®</sup>-core-based CoWoS<sup>®</sup> Chiplet Design for High Performance Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.
IEEE J. Solid State Circuits, 2014

A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Effects of music tempo and task difficulty on multi-attribute decision-making: An eye-tracking approach.
Comput. Hum. Behav., 2009

An Effective Demosaicking and Zooming Algorithm for CFA Images.
Proceedings of the 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), 2008

TFRP: An efficient microaggregation algorithm for statistical disclosure control.
J. Syst. Softw., 2007