Chin-Hua Wen
According to our database1,
Chin-Hua Wen authored at least 6 papers
between 2010 and 2026.
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Bibliography
2026
8.2 A 32Gb/s 12.35Tb/s/mm<sup>2</sup> 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 0.296pJ/bit 17.9Tb/s/mm<sup>2</sup> Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2020
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2016
Proceedings of the 11th IEEE Annual International Conference on Nano/Micro Engineered and Molecular Systems, 2016
2010
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010