Chi-Chao Wang

According to our database1, Chi-Chao Wang authored at least 9 papers between 2008 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
The potential of Fe-FET for robust design under variations: A compact modeling study.
Microelectron. J., 2012

Leakage reduction through optimization of regular layout parameters.
Microelectron. J., 2012

2010
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Workload-adaptive process tuning strategy for power-efficient multi-core processors.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Simulation of random telegraph Noise with 2-stage equivalent circuit.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
The Predictive Technology Model in the Late Silicon Era and Beyond.
Found. Trends Electron. Des. Autom., 2009

Modeling of layout-dependent stress effect in CMOS design.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Pathfinding for 22nm CMOS designs using Predictive Technology Models.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Design rule optimization of regular layout for leakage reduction in nanoscale design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008


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