Jungseob Lee
Orcid: 0000-0002-9431-6342
According to our database1,
Jungseob Lee
authored at least 22 papers
between 2007 and 2023.
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Bibliography
2023
Expert Syst. Appl., December, 2023
Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics: System Demonstrations, 2023
2022
Language Chameleon: Transformation analysis between languages using Cross-lingual Post-training based on Pre-trained language models.
CoRR, 2022
Empirical study on BlenderBot 2.0 Errors Analysis in terms of Model, Data and User-Centric Approach.
CoRR, 2022
K-NCT: Korean Neural Grammatical Error Correction Gold-Standard Test Set Using Novel Error Type Classification Criteria.
IEEE Access, 2022
Empirical Analysis of Noising Scheme based Synthetic Data Generation for Automatic Post-editing.
Proceedings of the Thirteenth Language Resources and Evaluation Conference, 2022
QUAK: A Synthetic Quality Estimation Dataset for Korean-English Neural Machine Translation.
Proceedings of the 29th International Conference on Computational Linguistics, 2022
2017
Topological Entropy Dimension and Directional Entropy Dimension for ℤ<sup>2</sup>-Subshifts.
Entropy, 2017
2014
Fast detection of high-order epistatic interactions in genome-wide association studies using information theoretic measure.
Comput. Biol. Chem., 2014
Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2012
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG.
IEEE Trans. Very Large Scale Integr. Syst., 2012
2011
Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011
Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Optimizing total power of many-core processors considering voltage scaling limit and process variations.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Statistical static timing analysis considering leakage variability in power gated designs.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.
Proceedings of the 46th Design Automation Conference, 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007