Hamid Reza Ghasemi
According to our database1, Hamid Reza Ghasemi authored at least 12 papers between 2003 and 2016.
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VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Cost-effective power delivery to support per-core voltage domains for power-constrained processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC.
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003