Takashi Sato

According to our database1, Takashi Sato
  • authored at least 149 papers between 1980 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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On csauthors.net:

Bibliography

2017
RTN in Scaled Transistors for On-Chip Random Seed Generation.
IEEE Trans. VLSI Syst., 2017

Scalable Device Array for Statistical Characterization of BTI-Related Parameters.
IEEE Trans. VLSI Syst., 2017

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation.
IEICE Transactions, 2017

Reverse mathematics and order theoretic fixed point theorems.
Arch. Math. Log., 2017

Comparative study of path selection and objective function in replacing NBTI mitigation logic.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

SCAM: Secured content addressable memory based on homomorphic encryption.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations.
Proceedings of the 54th Annual Design Automation Conference, 2017

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Efficient circuit failure probability calculation along product lifetime considering device aging.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability.
IEICE Transactions, 2016

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling.
IEICE Transactions, 2016

Roles and Effects of Human Network of Supporting Experts out of Niigata University to Practical Engineering Education.
iJEP, 2016

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing.
J. Electronic Testing, 2016

OKSAT at NTCIR-12 Short Text Conversation Task: Priority to Short Comments, Filtering by Characteristic Words and Topic Classification.
Proceedings of the 12th NTCIR Conference on Evaluation of Information Access Technologies, 2016

Nonlinear delay-table approach for full-chip NBTI degradation prediction.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Efficient transistor-level timing yield estimation via line sampling.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor.
Proceedings of the 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2016

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Farsightedly stable tariffs.
Mathematical Social Sciences, 2015

Introduction to: Special Issue on Cross-Layer System Design.
JETC, 2015

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs.
IEICE Transactions, 2015

Robust in-hand manipulation of variously sized and shaped objects.
Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A Variability-Aware Adaptive Test Flow for Test Quality Improvement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Reverse mathematics and Isbell's zig-zag theorem.
Math. Log. Q., 2014

State-Dependence of On-Chip Power Distribution Network Capacitance.
IEICE Transactions, 2014

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination.
IEICE Transactions, 2014

Automation of Model Parameter Estimation for Random Telegraph Noise.
IEICE Transactions, 2014

Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis.
IEICE Transactions, 2014

Sentence-based Plagiarism Detection focusing on Nouns and Part-of-Speech Structure.
Proceedings of the New Trends in Software Methodologies, Tools and Techniques, 2014

OKSAT at NTCIR-11 RecipeSearch: Categorization and Expansion of Search Terms in Topics.
Proceedings of the 11th NTCIR Conference on Evaluation of Information Access Technologies, 2014

OKSAT at NTCIR-11 Temporalia: Plural Sets of Search Terms for a Topic.
Proceedings of the 11th NTCIR Conference on Evaluation of Information Access Technologies, 2014

Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

SML# in industry: a practical ERP system development.
Proceedings of the 19th ACM SIGPLAN international conference on Functional programming, 2014

Sensorless estimation of global device-parameters based on Fmax testing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Variability in device degradations: Statistical observation of NBTI for 3996 transistors.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element.
IEICE Transactions, 2013

Device-Parameter Estimation through IDDQ Signatures.
IEICE Transactions, 2013

A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis.
IEICE Transactions, 2013

Osaka Kyoiku University at NTCIR-10 CrossLink-2: Link Filtering by Title Tag of Corpus as a Dictionary.
Proceedings of the 10th NTCIR Conference on Evaluation of Information Access Technologies, 2013

High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Multi-trap RTN parameter extraction based on Bayesian inference.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Sensor prediction and grasp stability evaluation for in-hand manipulation.
Proceedings of the 2013 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2013

Unitron: Loadable Kernel Module for Adding Real-Time Functionality of uITRON to UNIX Kernel.
Proceedings of the First International Symposium on Computing and Networking, 2013

Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array.
Proceedings of the Design, Automation and Test in Europe, 2013

A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Realization of frequency-domain circuit analysis through random walk.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Statistical simulation methods for circuit performance analysis.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Existence of equilibria in quantum Bertrand-Edgeworth duopoly game.
Quantum Information Processing, 2012

A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits.
IEICE Transactions, 2012

Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis.
IEICE Transactions, 2012

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method.
IEICE Transactions, 2012

A Bayesian-based process parameter estimation using IDDQ current signature.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Flexible Group Key Exchange with On-demand Computation of Subgroup Keys Supporting Subgroup Key Randomization.
Proceedings of the SECRYPT 2012, 2012

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Physics matters: statistical aging prediction under trapping/detrapping.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Statistical aging under dynamic voltage scaling: A logarithmic model approach.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
MEF/ELF4 transactivation by E2F1 is inhibited by p53.
Nucleic Acids Research, 2011

A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

NTCIR-9 GeoTime at Osaka Kyoiku University - Toward Automatic Extraction of Place/Time Terms -.
Proceedings of the 9th NTCIR Workshop Meeting on Evaluation of Information Access Technologies: Information Retrieval, 2011

A fully pipelined implementation of Monte Carlo based SSTA on FPGAs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Acceleration of random-walk-based linear circuit analysis using importance sampling.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

T-Robust Scalable Group Key Exchange Protocol with O(logn) Complexity.
Proceedings of the Information Security and Privacy - 16th Australasian Conference, 2011

2010
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A Universal Equivalent Circuit Model for Ceramic Capacitors.
IEICE Transactions, 2010

A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation.
IEICE Transactions, 2010

A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.
IEICE Transactions, 2010

Impact of Self-Heating in Wire Interconnection on Timing.
IEICE Transactions, 2010

Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures.
IEICE Transactions, 2010

Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence.
IEICE Transactions, 2010

Path clustering for adaptive test.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Application of generalized scattering matrix for prediction of power supply noise.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

NTCIR-8 GeoTime at Osaka Kyoiku University: Hierarchical Index for Geographic Retrieval.
Proceedings of the 8th NTCIR Workshop Meeting on Evaluation of Information Access Technologies: Information Retrieval, 2010

Linear time calculation of state-dependent power distribution network capacitance.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Robust importance sampling for efficient SRAM yield analysis.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Scan based process parameter estimation through path-delay inequalities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Decomposition of drain-current variation into gain-factor and threshold voltage variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept.
IEICE Transactions, 2009

One-Shot Voltage-Measurement Circuit Utilizing Process Variation.
IEICE Transactions, 2009

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.
IEICE Transactions, 2009

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Transactions, 2009

Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits.
IEICE Transactions, 2009

Physical design challenges to nano-CMOS circuits.
IEICE Electronic Express, 2009

An Adaptive Test for Parametric Faults Based on Statistical Timing Information.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress.
IEICE Transactions, 2008

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis.
IEICE Transactions, 2008

Timing Analysis Considering Temporal Supply Voltage Fluctuation.
IEICE Transactions, 2008

Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network.
IEICE Transactions, 2008

Decoupling capacitance allocation for timing with statistical noise model and timing analysis.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Electrodynamic Suspension and Stability of a Charged Droplet in Quadrupole Electrode.
Proceedings of the Industry Applications Society Annual Meeting, 2008

Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
Proceedings of the 45th Design Automation Conference, 2008

Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement.
IEEE Trans. on Circuits and Systems, 2007

Proposal of Metrics for SSTA Accuracy Evaluation.
IEICE Transactions, 2007

Adaptable wire-length distribution with tunable occupation probability.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Weakness Identification for Effective Repair of Power Distribution Network.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

NTCIR-6 CLIR Experiments at Osaka Kyoiku University - Term Expansion Using Online Dictionaries and Weighting Score by Term Variety.
Proceedings of the 6th NTCIR Workshop Meeting on Evaluation of Information Access Technologies: Information Retrieval, 2007

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Improvement of power distribution network using correlation-based regression analysis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A Multi-Drop Transmission-Line Interconnect in Si LSI.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature.
IEICE Transactions, 2006

A Method to Derive SSO Design Rule Considering Jitter Constraint.
IEICE Transactions, 2006

A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Paravie: dance entertainment system for everyone to express oneself with movement.
Proceedings of the International Conference on Advances in Computer Entertainment Technology, 2006

2005
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design.
IEICE Transactions, 2005

Successive Pad Assignment for Minimizing Supply Voltage Drop.
IEICE Transactions, 2005

The carbohydrate sequence markup language (CabosML): an XML description of carbohydrate structures.
Bioinformatics, 2005

NTCIR-5 WEB Navi-2 Experiments at Osaka Kyoiku University - Page, Anchor and Title Indexing, and In-link Count, Inter Page and Inter Site Link Analyses.
Proceedings of the Fifth NTCIR Workshop Meeting on Evaluation of Information Access Technologies: Information Retrieval, 2005

Optimization of damping control parameters for cycle time reduction in clutch assembly.
Proceedings of the 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2005

Static and Dynamic Scoring by Web Page Grouping.
Proceedings of the 21st International Conference on Data Engineering Workshops, 2005

On-chip thermal gradient analysis and temperature flattening for SoC design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Timing analysis considering temporal supply voltage fluctuation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Probabilistic crosstalk delay estimation for ASICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

NTCIR-4 PATENT Experiments at Osaka Kyoiku University - Gram-Based Passage Index and Essential Words.
Proceedings of the Fourth NTCIR Workshop on Research in Information Access Technologies Information Retrieval, 2004

NTCIR-4 WEB Experiments at Osaka Kyoiku University - Static/Dynamic Scoring Using Link Structure Analysis and Web Page Grouping.
Proceedings of the Fourth NTCIR Workshop on Research in Information Access Technologies Information Retrieval, 2004

Dynamic Social Simulation with Multi-agents Having Internal Dynamics.
Proceedings of the New Frontiers in Artificial Intelligence - JSAI 2003 and JSAI 2004 Conferences and Workshops, Niigata, Japan, June 23-27, 2003 and Kanazawa, Japan, May 31, 2004

Design of damping control parameters for peg-in-hole by industrial manipulator considering cycle time.
Proceedings of the 2004 IEEE/RSJ International Conference on Intelligent Robots and Systems, Sendai, Japan, September 28, 2004

2003
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Approximate formulae approach for efficient inductance extraction.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

NTCIR-3 PAT Experiments at Osaka Kyoiku University: Long Gram-based Index and Essential Words.
Proceedings of the Third NTCIR Workshop on Research in Information Retrieval, 2002

NTCIR-3 WEB Experiments at Osaka Kyoiku University - Towards Index Partitioning and Parallel Retrieval.
Proceedings of the Third NTCIR Workshop on Research in Information Retrieval, 2002

NTCIR-3 CLIR Experiments at Osaka Kyoiku University - Comparison of Gram-based Indices.
Proceedings of the Third NTCIR Workshop on Research in Information Retrieval, 2002

2001
Structure Design of Neural Networks Using Genetic Algorithms.
Complex Systems, 2001

NTCIR-2 Experiments Using Long Gram Based Indices.
Proceedings of the Third Second Workshop Meeting on Evaluation of Chinese & Japanese Text Retrieval and Text Summarization, 2001

Application of IEC61131-3 for semiconductor processing equipment.
Proceedings of 8th IEEE International Conference on Emerging Technologies and Factory Automation, 2001

1996
Fast Full Text Search Using Tree Structured[TS] File.
Proceedings of the Prague Stringology Club Workshop 1996, 1996

ChangFast Arbitrary String Search from Large Data.
CODAS, 1996

1992
An Efficient Implementation of Trie Structures.
Softw., Pract. Exper., 1992

1991
Order preserving code having a search tree.
Systems and Computers in Japan, 1991

1989
Numerical computation of large partial differential equations on memory hierarchy.
Systems and Computers in Japan, 1989

An efficient algorithm for layout compaction problem with symmetry constraints.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Contextual knowledge for summarizing Japanese texts and generating English sentences.
Proceedings of the Twelfth International Computer Software and Applications Conference, 1988

An efficient digital search algorithm by using a double-array structure.
Proceedings of the Twelfth International Computer Software and Applications Conference, 1988

1983
PACS: A Parallel Microprocessor Array for Scientific Calculations
ACM Trans. Comput. Syst., 1983

Generalization of Floyd's Model on Permuting Information in Idealized Two-Level Storage.
Inf. Process. Lett., 1983

Transposition of Large Tabular Data Structures with Applications to Physical Database Organization.
Acta Inf., 1983

Transposition of Large Tabular Data Structures with Applications to Physical Database Organization.
Acta Inf., 1983

1980
A conversational decision support system for resource allocation without explicit objective function.
Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980


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