Ching-Chuen Jong

Orcid: 0000-0003-1178-9062

According to our database1, Ching-Chuen Jong authored at least 44 papers between 1994 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Non-iterative division circuit design with accuracy and performance trade-off based on mixed integer linear programming approach.
Microelectron. J., 2022

2019
A High-Throughput VLSI Architecture for Real-Time Full-HD Gradient Guided Image Filter.
IEEE Trans. Circuits Syst. Video Technol., 2019

2018
Range Mapping - A Fresh Approach to High Accuracy Mitchell-Based Logarithmic Conversion Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2016
ANN Predicted Apps-Usage Aware Linux Scheduler for Asymmetrical Multi Cluster SoC.
J. Softw., 2016

A VLSI architecture for real-time gradient guided image filtering.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Linux apps-usage-driven power dissipation-aware scheduler.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Unified Mitchell-Based Approximation for Efficient Logarithmic Conversion Circuit.
IEEE Trans. Computers, 2015

A curve fitting approach for non-iterative divider design with accuracy and performance trade-off.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Memory-efficient discrete wavelet transform architecture based on wordlength optimization.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Apps-usage driven energy management for multicore mobile computing systems.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013
A Memory-Efficient High-Throughput Architecture for Lifting-Based Multi-Level 2-D DWT.
IEEE Trans. Signal Process., 2013

A Memory-Efficient Scalable Architecture for Lifting-Based Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Memory-Efficient Tables-and-Additions Method for Accurate Computation of Elementary Functions.
IEEE Trans. Computers, 2013

Non-iterative high speed division computation based on Mitchell logarithmic method.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Scalable linear array architectures for matrix inversion using Bi-z CORDIC.
Microelectron. J., 2012

A fast and compact circuit for integer square root computation based on Mitchell logarithmic method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
A novel counter-based low complexity inner-product architecture for high speed inputs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High accuracy binary logarithmic conversion using range mapping for DSP applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Floorplan-Driven Multivoltage High-Level Synthesis.
VLSI Design, 2009

Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Contention Resolution - A New Approach to Versatile Subexpressions Sharing in Multiple Constant Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A low complexity modulo 2<sup>n</sup>+1 squarer design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

High-speed and low-power serial accumulator for serial/parallel multiplier.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis.
Microelectron. J., 2007

Hamming weight pyramid - A new insight into canonical signed digit representation and its applications.
Comput. Electr. Eng., 2007

2006
A new integrated approach to the design of low-complexity FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Contention resolution algorithm for common subexpression elimination in digital filter design.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

I<sup>2</sup>CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression elimination.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A new contention resolution algorithm for the design of minimal logic depth multiplierless filters.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

HWP: a new insight into canonical signed digit.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Efficient algorithms for common subexpression elimination in digital filter design.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2002
Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis.
J. Comput. Sci. Technol., 2002

2000
Functional area lower bound and upper bound on multicomponentselection for interval scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999
A lower bound on general minimal resource interval scheduling with arbitrary component selection.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
FPGA implementation of a digital IQ demodulator using VHDL.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

1994
Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


  Loading...