Jeremy Yung Shern Low

According to our database1, Jeremy Yung Shern Low authored at least 15 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Erratum to "Efficient VLSI Implementation of 2<sup>n</sup> Scaling of Signed Integer in RNS {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1}".
IEEE Trans. Very Large Scale Integr. Syst., 2016

2013
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A signed integer programmable power-of-two scaler for {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1} RNS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A VLSI Efficient Programmable Power-of-Two Scaler for 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1 RNS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A fast and compact circuit for integer square root computation based on Mitchell logarithmic method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A unified {2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1} RNS scaler with dual scaling constants.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2011

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2<sup>n</sup> - 1, 2<sup>n</sup>, 2<sup>n</sup> + 1.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A new RNS scaler for {2<sup>n</sup> - 1, 2<sup>n</sup>, 2<sup>n</sup> + 1}.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A novel counter-based low complexity inner-product architecture for high speed inputs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008
A full current-mode sense amplifier for low-power SRAM applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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