Andreas Herkersdorf

According to our database1, Andreas Herkersdorf authored at least 196 papers between 1991 and 2020.

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Bibliography

2020
Combinatorial Auctions for Temperature-Constrained Resource Management in Manycores.
IEEE Trans. Parallel Distributed Syst., 2020

Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs.
ACM Trans. Design Autom. Electr. Syst., 2020

Self-aware Cyber-Physical Systems.
ACM Trans. Cyber Phys. Syst., 2020

A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores.
IEEE Trans. Computers, 2020

AXES: Approximation Manager for Emerging Memory Architectures.
CoRR, 2020

Fine-Grained Power Modeling of Multicore Processors Using FFNNs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Inter-Server RSS: Extending Receive Side Scaling for Inter-Server Workload Distribution.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

HyVE: A Hybrid Voting-based Eviction Policy for Caches.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs.
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

2019
The Information Processing Factory: Organization, Terminology, and Definitions.
CoRR, 2019

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

APEC: improved acknowledgement prioritization through erasure coding in bufferless NoCs.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Channel mapping strategies for effective protection switching in fail-operational hard real-time NoCs.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

SOSA: Self-Optimizing Learning with Self-Adaptive Control for Hierarchical System-on-Chip Management.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

NEMESYS: near-memory graph copy enhanced system-software.
Proceedings of the International Symposium on Memory Systems, 2019

Multicore Power Estimation using Independent Component Analysis Based Modeling.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs.
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

The information processing factory: a paradigm for life cycle management of dependable systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

Network Coding in Networks-on-Chip with Lossy Links.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC.
Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

Cryptographic Hashing in P4 Data Planes.
Proceedings of the 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2019

2018
Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS.
Proc. IEEE, 2018

Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Design methodologies for enabling self-awareness in autonomous systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
Efficient task spawning for shared memory and message passing in many-core architectures.
J. Syst. Archit., 2017

DiaSys: Improving SoC insight through on-chip diagnosis.
J. Syst. Archit., 2017

Region based cache coherence for tiled MPSoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A Divide and Conquer State Grouping Method for Bitmap Based Transition Compression.
Proceedings of the 18th International Conference on Parallel and Distributed Computing, 2017

Adaptive Reliability for Fault Tolerant Multicore Systems.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Self-awareness in autonomous automotive systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A non-intrusive, operating system independent spinlock profiler for embedded multicore systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
MPSoC application resilience by hardware-assisted communication virtualization.
Microelectron. Reliab., 2016

ANN Predicted Apps-Usage Aware Linux Scheduler for Asymmetrical Multi Cluster SoC.
J. Softw., 2016

Dark silicon management: an integrated and coordinated cross-layer approach.
it Inf. Technol., 2016

Improving SoC Insight Through On-Chip Diagnosis.
CoRR, 2016

TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters.
Proceedings of the High Performance Computing - 31st International Conference, 2016

A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Hardware acceleration of signature matching through multi-layer transition bit masking.
Proceedings of the 26th International Telecommunication Networks and Applications Conference, 2016

What happens on an MPSoC stays on an MPSoC - unfortunately!
Proceedings of the International Symposium on Integrated Circuits, 2016

Linux apps-usage-driven power dissipation-aware scheduler.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Conquering MPSoC complexity with principles of a self-aware information processing factory.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Disaggregated FPGAs: Network Performance Comparison against Bare-Metal Servers, Virtual Machines and Linux Containers.
Proceedings of the 2016 IEEE International Conference on Cloud Computing Technology and Science, 2016

DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

Estimation of End-to-End Packet Error Rates for NoC Multicasts.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance.
J. Syst. Archit., 2015

Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures.
J. Syst. Archit., 2015

Adaptive multi-layer techniques for increased system dependability.
it Inf. Technol., 2015

Enabling FPGAs in Hyperscale Data Centers.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

Sharer status-based caching in tiled multiprocessor systems-on-chip.
Proceedings of the Symposium on High Performance Computing, 2015

Monitoring of I/O for safety-critical systems using PCI express advanced error reporting.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015

Fail-operational in safety-related automotive multi-core systems.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015

A hardware-based multi-objective thread mapper for tiled manycore architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

IOMPU: Spatial Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using Non-transparent Bridges.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Design and Evaluation of a Low-Latency AVB Ethernet Endpoint Based on ARM SoC.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-Chip.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Network Interface with Task Spawning Support for NoC-Based DSM Architectures.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

SgInt: Safeguarding Interrupts for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using Non Transparent Bridges.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

Fault-tolerant communication in invasive networks on chip.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV.
Proceedings of the 8th IEEE International Conference on Cloud Computing, 2015

2014
Spatial and temporal isolation of virtual CAN controllers.
SIGBED Rev., 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014

A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs.
CoRR, 2014

An automotive specific MILP model targeting power-aware function partitioning.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A network virtualization approach for performance isolation in controller area network (CAN).
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Deep packet inspection in residential gateways and routers: Issues and challenges.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Apps-usage driven energy management for multicore mobile computing systems.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN).
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Dependable task and communication migration in tiled manycore system-on-chip.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hardware virtualization support for shared resources in mixed-criticality multicore systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

System integration - The bridge between More than Moore and More Moore.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Distributed cooperative shared last-level caching in tiled multiprocessor system on chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

CAP: Communication Aware Programming.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Performance Isolation Exposure in Virtualized Platforms with PCI Passthrough I/O Sharing.
Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014

Temporal Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using PCIe SR-IOV.
Proceedings of the ARCS 2014, 2014

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure.
Proceedings of the ARCS 2014, 2014

2013
Virtual networks - distributed communication resource management.
ACM Trans. Reconfigurable Technol. Syst., 2013

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.
IEEE Micro, 2013

Virtualized and fault-tolerant inter-layer-links for 3D-ICs.
Microprocess. Microsystems, 2013

Multicore Enablement for Embedded and Cyber Physical Systems (Dagstuhl Seminar 13052).
Dagstuhl Reports, 2013

Invasive Computing - Common Terms and Granularity of Invasion
CoRR, 2013

Open Tiled Manycore System-on-Chip
CoRR, 2013

Evaluation of hop count advantages of network-coded 2D-mesh NoCs.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Hardware Supported Adaptive Data Collection for Networks on Chip.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Potentials and Challenges for Multi-Core Processors in Robotic Applications.
Proceedings of the 43. Jahrestagung der Gesellschaft für Informatik, 2013

A Design Space Exploration Framework For Automotive Embedded Systems And Their Power Management.
Proceedings of the 27th European Conference on Modelling and Simulation, 2013

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Hardware-Based I/O Virtualization for Mixed Criticality Real-Time Systems Using PCIe SR-IOV.
Proceedings of the 16th IEEE International Conference on Computational Science and Engineering, 2013

HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

Self-virtualized CAN Controller for Multi-core Processors in Real-Time Applications.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013

2012
Benefits of selective packet discard in networks-on-chip.
ACM Trans. Archit. Code Optim., 2012

Multicore Enablement for Automotive Cyber Physical Systems.
it Inf. Technol., 2012

Multicore enablement for Cyber Physical Systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

System-level software performance simulation considering out-of-order processor execution.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A framework for Open Tiled Manycore System-On-Chip.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An integrated simulation framework for invasive computing.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Dependable embedded systems: The German research foundation DFG priority program SPP 1500.
Proceedings of the 17th IEEE European Test Symposium, 2012

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined Radios.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A low-overhead monitoring ring interconnect for MPSoC parameter optimization.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Virtual platforms: Breaking new grounds.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A Real-Time Capable Virtualized Information and Communication Technology Infrastructure for Automotive Systems.
Proceedings of the Advances in Real-Time Systems (to Georg Färber on the occasion of his appointment as Professor Emeritus at TU München after leading the Lehrstuhl für Realzeit-Computersysteme for 34 illustrious years)., 2012

Invasive manycore architectures.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
Advanced Packet Segmentation and Buffering Algorithms in Network Processors.
Trans. High Perform. Embed. Archit. Compil., 2011

Organic Computing - Design of Self-Organizing Systems (Dagstuhl Seminar 11181).
Dagstuhl Reports, 2011

Context-aware compiled simulation of out-of-order processor behavior based on atomic traces.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Accelerating collective communication in message passing on manycore System-on-Chip.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Applying autonomic principles for workload management in multi-core systems on chip.
Proceedings of the 8th International Conference on Autonomic Computing, 2011

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

An approach to improve accuracy of source-level TLMs of embedded software.
Proceedings of the Design, Automation and Test in Europe, 2011


Invasive Computing: An Overview.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

Applying ASoC to Multi-core Applications for Workload Management.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

Autonomic System on Chip Platform.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

Combining Software and Hardware LCS for Lightweight On-chip Learning.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

2010
Software performance simulation strategies for high-level embedded system design.
Perform. Evaluation, 2010

High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks.
Proceedings of the NOCS 2010, 2010

Towards Scalability and Reliability of Autonomic Systems on Chip.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

Combining Software and Hardware LCS for Lightweight On-Chip Learning.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

An Application-Aware Load Balancing Strategy for Network Processors.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Architectural Vulnerability Factor Estimation with Backwards Analysis.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

A rapid prototyping system for error-resilient multi-processor systems-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

Autonomic Workload Management for Multi-core Processor Systems.
Proceedings of the Architecture of Computing Systems, 2010

A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces.
Proceedings of the Architecture of Computing Systems, 2010

A folded pipeline network processor architecture for 100 Gbit/s networks.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
Flow Analysis on Intermediate Source Code for WCET Estimation of Compiler-Optimized Programs.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

NoC topology exploration for mobile multimedia applications.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

SysCOLA: a framework for co-development of automotive software and system platform.
Proceedings of the 46th Design Automation Conference, 2009

An efficient approach for system-level timing simulation of compiler-optimized embedded software.
Proceedings of the 46th Design Automation Conference, 2009

2008
A Processing Path Dispatcher in Network Processor MPSoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

SciSim: a software performance estimation framework using source code instrumentation.
Proceedings of the 7th International Workshop on Software and Performance, 2008

Improving memory subsystem performance in network processors with smart packet segmentation.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

FlexPath NP - A network processor architecture with flexible processing paths.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

A Simulation Approach for Performance Validation during Embedded Systems Design.
Proceedings of the Leveraging Applications of Formal Methods, 2008

Learning Classifier Tables for Autonomic Systems on Chip.
Proceedings of the 38. Jahrestagung der Gesellschaft für Informatik, Beherrschbare Systeme, 2008

Workshop "Adaptive and Organic Systems".
Proceedings of the 38. Jahrestagung der Gesellschaft für Informatik, Beherrschbare Systeme, 2008



A Model Driven Development Approach for Implementing Reactive Systems in Hardware.
Proceedings of the Forum on specification and Design Languages, 2008

Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Determining the Fidelity of Hardware-In-the-Loop Simulation Coupling Systems.
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

Buffer allocation for advanced packet segmentation in Network Processors.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

A Hardware Packet Re-Sequencer Unit for Network Processors.
Proceedings of the Architecture of Computing Systems, 2008

2007
Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications.
J. Syst. Archit., 2007

Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme).
it Inf. Technol., 2007

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Organic Computing at the System on Chip Level.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs.
Proceedings of the Biologically Inspired Cooperative Computing, 2006

An Architecture for Runtime Evaluation of SoC Reliability.
Proceedings of the 36. Jahrestagung der Gesellschaft für Informatik, 2006

Performance evaluation for system-on-chip architectures using trace-based transaction level simulation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

AutoVision: flexible processor architecture for video-assisted driving.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Reconfigurable Processing Units vs. Reconfigurable Interconnects.
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

2005
Robust header compression (ROHC) in next-generation network processors.
IEEE/ACM Trans. Netw., 2005

TAPES - Trace-based architecture performance evaluation with SystemC.
Des. Autom. Embed. Syst., 2005

Towards a Framework and a Design Methodology for Autonomic SoC.
Proceedings of the Second International Conference on Autonomic Computing (ICAC 2005), 2005

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization.
Proceedings of the 2005 Design, 2005

FlexPath NP: a network processor concept with application-driven flexible processing paths.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Adaptable DSP Functions for Dynamically Reconfigurable Communication Systems.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

Towards a Framework and a Design Methodology for Autonomous SoC.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
Towards a Framework and a Design Methodology for Autonomic Integrated Systems.
Proceedings of the 34. Jahrestagung der Gesellschaft für Informatik, 2004

Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing.
Proceedings of the ARCS 2004, 2004

A Comparison of Parallel Programming Models of Network Processors.
Proceedings of the ARCS 2004, 2004

2003
IBM PowerNP network processor: Hardware, software, and applications.
IBM J. Res. Dev., 2003

Design methodology for a modular service-driven network processor architecture.
Comput. Networks, 2003

Performance evaluation of network processor architectures: combining simulation with analytical estimation.
Comput. Networks, 2003

2002
Early analysis tools for system-on-a-chip design.
IBM J. Res. Dev., 2002

2000
Design Methodology for a Large Communication Chip.
IEEE Des. Test Comput., 2000

1999
A scalable modular architecture for SDH/SONET technology.
Proceedings of the International Conference On Computer Communications and Networks (ICCCN 1999), 1999

1995
Route Discovery for Multistage Fabrics in ATM Switching Nodes.
Perform. Evaluation, 1995

1993
Fast Connection Establishment in Large-Scale Networks.
Proceedings of the Proceedings IEEE INFOCOM '93, The Conference on Computer Communications, Twelfth Annual Joint Conference of the IEEE Computer and Communications Societies, Networking: Foundation for the Future, San Francisco, CA, USA, March 28, 1993

Route Discovery in Multistage Switch Fabrics.
Proceedings of the High Speed Networks and Their Performance, 1993

1991
A method and a tool for the real-time evaluation of fast packet switching systems.
PhD thesis, 1991


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