Ching-Yu Chin

According to our database, Ching-Yu Chin authored at least 12 papers between 2009 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

An analytical placer for heterogeneous FPGAs via rough-placed packing.

Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2015

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation.

Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability.

Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014

Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function.

Shih-Ying Sean Liu, Ren-Guo Luo, Suradeth Aroonsantidecha, Ching-Yu Chin, Hung-Ming Chen

IEEE Trans. Very Large Scale Integr. Syst., 2014

Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation.

Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin

ACM Trans. Design Autom. Electr. Syst., 2014

2013

Escaped Boundary Pins Routing for High-Speed Boards.

Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Efficient analog layout prototyping by layout reuse with routing preservation.

Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

A fast thermal aware placement with accurate thermal analysis based on Green function.

Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A Novel Test Flow for One-Time-Programming Applications of NROM Technology.

Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang

IEEE Trans. Very Large Scale Integr. Syst., 2011

On routing fixed escaped boundary pins for high speed boards.

Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Mathematical yield estimation for two-dimensional-redundancy memory arrays.

Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Fault models for embedded-DRAM macros.

Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin

Proceedings of the 46th Design Automation Conference, 2009