Mango Chia-Tso Chao

Orcid: 0000-0002-7299-9015

According to our database¹, Mango Chia-Tso Chao authored at least 72 papers between 1999 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2023

CNN-Based Stochastic Regression for IDDQ Outlier Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

DRC Violation Prediction After Global Route Through Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., September, 2023

Test Generation for Defect-Based Faults of Scan Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Outlier Detection for Analog Tests Using Deep Learning Techniques.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Test Methodology for Defect-Based Bridge Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Methodology of Generating Timing-Slack-Based Cell-Aware Tests.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Rule Generation for Classifying SLT Failed Parts.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Improving Cell-Aware Test for Intra-Cell Short Defects.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020

CNN-based Stochastic Regression for IDDQ Outlier Identification.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Test Methodology for Defect-based Bridge Faults.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Power Distribution Network Generation for Optimizing IR-Drop Aware Timing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Layout-Based Dual-Cell-Aware Tests.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2018

A Model-Based-Random-Forest Framework for Predicting V<sub>t</sub> Mean and Variance Based on Parallel I<sub>d</sub> Measurement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

DVFS Binning Using Machine-Learning Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Fast WAT test structure for measuring Vt variance based on latch-based comparators.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Methodology of generating dual-cell-aware tests.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Predicting Vt mean and variance from parallel Id measurement with model-fitting technique.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Random pattern generation for post-silicon validation of DDR3 SDRAM.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Statistical techniques for predicting system-level failure using stress-test data.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Testing methods for quaternary content addressable memory using charge-sharing sensing scheme.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs.

[BibT_eX]

[DOI]

Chen-Wei Lin

Mango Chia-Tso Chao

Chih-Chieh Hsu

IEEE Trans. Very Large Scale Integr. Syst., 2014

Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer.

[BibT_eX]

[DOI]

Wen-Hsiang Chang

Mango Chia-Tso Chao

Shi-Hao Chen

IEEE Trans. Very Large Scale Integr. Syst., 2014

Testing methods for a write-assist disturbance-free dual-port SRAM.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2013

Power-Up Sequence Control for MTCMOS Designs.

[BibT_eX]

[DOI]

Shi-Hao Chen

Youn-Long Lin

Mango Chia-Tso Chao

IEEE Trans. Very Large Scale Integr. Syst., 2013

Fault Models and Test Methods for Subthreshold SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Testing of a low-VMIN data-aware dynamic-supply 8T SRAM.

[BibT_eX]

[DOI]

Chen-Wei Lin

Chin-Yuan Huang

Mango Chia-Tso Chao

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs.

[BibT_eX]

[DOI]

Chen-Wei Lin

Mango Chia-Tso Chao

Chih-Chieh Hsu

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Testing retention flip-flops in power-gated designs.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

Testing Methodology of Embedded DRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Testing strategies for a 9T sub-threshold SRAM.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Alternate hammering test for application-specific DRAMs and an industrial case study.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs.

[BibT_eX]

[DOI]

Yi-Ming Wang

Shi-Hao Chen

Mango Chia-Tso Chao

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs.

[BibT_eX]

[DOI]

Chen-Wei Lin

Mango C.-T. Chao

Yen-Shih Huang

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Novel Test Flow for One-Time-Programming Applications of NROM Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Design-for-debug layout adjustment for FIB probing and circuit editing.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Detecting stability faults in sub-threshold SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes.

[BibT_eX]

[DOI]

Yu-Ze Wu

Mango Chia-Tso Chao

ACM Trans. Design Autom. Electr. Syst., 2010

A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Theoretical analysis for low-power test decompression using test-slice duplication.

[BibT_eX]

[DOI]

Szu-Pang Mu

Mango Chia-Tso Chao

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Mask versus Schematic - an enhanced design-verification flow for first silicon success.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Fault models and test methods for subthreshold SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Mathematical yield estimation for two-dimensional-redundancy memory arrays.

[BibT_eX]

[DOI]

Mango Chia-Tso Chao

Ching-Yu Chin

Chen-Wei Lin

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Multiple-Fault Diagnosis Using Faulty-Region Identification.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A novel array-based test methodology for local process variation monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Power-switch routing for coarse-grain MTCMOS technologies.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Fault models for embedded-DRAM macros.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes.

[BibT_eX]

[DOI]

Yu-Ze Wu

Mango Chia-Tso Chao

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Testing Methodology of Embedded DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

A hybrid scheme for compacting test responses with unknown values.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Coverage loss by using space compactors in presence of unknown values.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Response shaper: a novel technique to enhance unknown tolerance for output response compaction.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

A clustering- and probability-based approach for time-multiplexed FPGA partitioning.

[BibT_eX]

[DOI]

Guang-Ming Wu

Mango Chia-Tso Chao

Yao-Wen Chang

Integr., 2004

Pattern Selection for Testing of Deep Sub-Micron Timing Defects.

[BibT_eX]

[DOI]

Mango Chia-Tso Chao

Li-C. Wang

Kwang-Ting Cheng

Proceedings of the 2004 Design, 2004

2001

Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1999

A clustering- and probability-based approach for time-multiplexed FPGA partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Mango Chia-Tso Chao

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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