Rei-Fu Huang

According to our database1, Rei-Fu Huang authored at least 23 papers between 2002 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Testing methods for quaternary content addressable memory using charge-sharing sensing scheme.
Proceedings of the 2015 IEEE International Test Conference, 2015

2014
Testing methods for a write-assist disturbance-free dual-port SRAM.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2013
Fault Models and Test Methods for Subthreshold SRAMs.
IEEE Trans. Computers, 2013

2012
Testing Methodology of Embedded DRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Alternate hammering test for application-specific DRAMs and an industrial case study.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Fault models and test methods for subthreshold SRAMs.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Fault models for embedded-DRAM macros.
Proceedings of the 46th Design Automation Conference, 2009

2008
Testing Methodology of Embedded DRAMs.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Raisin: Redundancy Analysis Algorithm Simulation.
IEEE Des. Test Comput., 2007

Economic Aspects of Memory Built-in Self-Repair.
IEEE Des. Test Comput., 2007

2005
A built-in self-repair design for RAMs with 2-D redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

MRAM Defect Analysis and Fault Modeli.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

On Test and Diagnostics of Flash Memories.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Fail Pattern Identification for Memory Built-In Self-Repair.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

SRAM delay fault modeling and test algorithm development.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A Processor-Based Built-In Self-Repair Design for Embedded Memories.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Defect Oriented Fault Analysis for SRAM.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002


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