Chongyun Zhang

Orcid: 0000-0001-5882-8781

According to our database¹, Chongyun Zhang authored at least 8 papers between 2021 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2026

A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, May, 2026

2025

A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, November, 2025

A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Solid State Circuits Lett., 2025

2024

A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm<sup>2</sup> area in 28-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 56-Gb/s PAM-4 Transmitter Using Silicon Photonic Microring Modulator in 40nm CMOS.

[BibT_eX]

[DOI]

Chongyun Zhang

Fuzhan Chen

C. Patrick Yue

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021

An Integrated System Evaluation Engine for Cross-Domain Simulation and Design Optimization of High-Speed 5G Millimeter-Wave Wireless SoCs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Chongyun Zhang

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Bibliography

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