Zilu Liu

Orcid: 0000-0003-1343-7845

According to our database1, Zilu Liu authored at least 16 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
BioSeek: A Design Generation Framework of Biosignal Processors with Large-Language Models for Edge Healthcare Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
A Compact 20-24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme.
IEEE J. Solid State Circuits, March, 2025

RIS-enhanced UAV-assisted transmission rate optimization with anti-jamming.
Phys. Commun., 2025

RC2DNet: Real-Time Cable Defect Detection Network Based on Small Object Feature Extraction.
Comput. Mater. Continua, 2025

Evaluation and Optimization of Glitch Power Based on Signal Transition Behavior of Logic Gates.
IEEE Access, 2025

Kilometer-Scale AI-Powered and Performance-Portable Earth System Model (AP3ESM) to Achieve Year-Scale Simulation Speed on Heterogeneous Supercomputers.
Proceedings of the International Conference for High Performance Computing, 2025

E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024
Role of hierarchical heterogeneity in shaping seizure onset dynamics: Insights from structurally-based whole-brain dynamical network models.
Commun. Nonlinear Sci. Numer. Simul., March, 2024

A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm<sup>2</sup> area in 28-nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 20-24-GHz DPSSPLL with Charge-Domain Bandwidth Optimization Scheme Achieving 61.3-fs RMS Jitter and -253-dB FoMJitter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and -248.6-dB FoMjitter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Design of Chip-to-PCB Matching Network for Millimeter-Wave On-Chip Transmitter and On-PCB Antenna.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
Synaptic Role in Facilitating Synchronous Theta Oscillations in a Hybrid Hippocampal Neuronal Network.
Frontiers Comput. Neurosci., 2022

2021
An Integrated System Evaluation Engine for Cross-Domain Simulation and Design Optimization of High-Speed 5G Millimeter-Wave Wireless SoCs.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

On-Chip Filter for Mitigating EMI-Related Common-Mode Noise in High-Speed PAM-4 Transmitter.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2019
Quantitative Analysis of Bitcoin Transferred in Bitcoin Exchange.
Proceedings of the Blockchain and Trustworthy Systems - First International Conference, 2019


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