Chu Shik Jhon

According to our database1, Chu Shik Jhon authored at least 66 papers between 1990 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
Bypassing method for STT-RAM based inclusive last-level cache.
Proceedings of the 2015 Conference on research in adaptive and convergent systems, 2015

2014
Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor.
IEICE Trans. Inf. Syst., 2014

Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor.
IEICE Trans. Inf. Syst., 2014

Adaptive cache compression for non-volatile memories in embedded system.
Proceedings of the 2014 Conference on Research in Adaptive and Convergent Systems, 2014

2013
Bypass Extended Stack Processing for Anti-Thrashing Replacement in Shared Last Level Cache of Chip Multiprocessors.
IEICE Trans. Inf. Syst., 2013

Data filter cache with word selection cache for low power embedded processor.
Proceedings of the Research in Adaptive and Convergent Systems, 2013

2012
Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors.
IEICE Trans. Inf. Syst., 2012

Low Power Instruction Cache with Word Selective Line Buffer.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
Time-Interleaved Access Control to Common RF Subsystem for Concurrent WiFi and WiMAX.
IEICE Trans. Commun., 2011

Throttling capacity sharing in private L2 caches of CMPs.
Proceedings of the Research in Applied Computation Symposium, 2011

Selective word reading for high performance and low power processor.
Proceedings of the Research in Applied Computation Symposium, 2011

2010
Dynamic register-renaming scheme for reducing power-density and temperature.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

2008
High-performance embedded branch predictor by combining branch direction history and global branch history.
IET Comput. Digit. Tech., 2008

Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
Torus Ring: improving performance of interconnection network by modifying hierarchical ring.
Parallel Comput., 2007

Dynamic per-branch history length adjustment to improve branch prediction accuracy.
Microprocess. Microsystems, 2007

2006
PP-cache: A partitioned power-aware instruction cache architecture.
Microprocess. Microsystems, 2006

Advanced High-Level Cache Management by Processor Access Information.
J. Inf. Sci. Eng., 2006

Adaptive Multi-Grain Remote Access Cache in Ring Based NUMA System.
J. Inf. Sci. Eng., 2006

An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors.
IEICE Trans. Inf. Syst., 2006

Robust Delay Control for Audio Streaming over Wireless Link.
IEICE Trans. Inf. Syst., 2006

Recovery Logics for Speculative Update Global and Local Branch History.
Proceedings of the Computer and Information Sciences, 2006

History Length Adjustable <i>gshare</i> Predictor for High-Performance Embedded Processor.
Proceedings of the Computational Science and Its Applications, 2006

Accuracy Enhancement by Selective Use of Branch History in Embedded Processor.
Proceedings of the Computational Science, 2006

On the Reliability of Drowsy Instruction Caches.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
Distance-aware L2 cache organizations for scalable multiprocessor systems.
J. Syst. Archit., 2005

A Power-Aware Branch Predictor by Accessing the BTB Selectively.
J. Comput. Sci. Technol., 2005

A Split L2 Data Cache for Scalable Cc-numa Multiprocessors.
J. Circuits Syst. Comput., 2005

Context-Dependent Phoneme Duration Modeling with Tree-Based State Tying.
IEICE Trans. Inf. Syst., 2005

The Impact of Branch Direction History Combined with Global Branch History in Branch Prediction.
IEICE Trans. Inf. Syst., 2005

Torus Ring: Improving Interconnection Network Performance by Modifying Hierarchical Ring.
IEICE Trans. Inf. Syst., 2005

Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic.
Proceedings of the Embedded Computer Systems: Architectures, 2005

First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption.
Proceedings of the Embedded Computer Systems: Architectures, 2005

An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information.
Proceedings of the Embedded and Ubiquitous Computing, 2005

An Innovative Instruction Cache for Embedded Processors.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Utilization of the On-Chip L2 Cache Area in CC-NUMA Multiprocessors for Applications with a Small Working Set.
IEICE Trans. Inf. Syst., 2004

Ownership-Lacking Line First Policy of Remote Access Cache in NUMA System.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

Level 1 & Victim Cache Management with Processor Reuse Information.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

A Novel Approach to Improve Cache Performance in Ring-Based Multiprocessors.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

Hybrid Technique for Reducing Energy Consumption in High Performance Embedded Processor.
Proceedings of the Embedded and Ubiquitous Computing, 2004

Adaptive Block Management for Victim Cache by Exploiting L1 Cache History Information.
Proceedings of the Embedded and Ubiquitous Computing, 2004

2002
A Second-Level Cache With the Distance-Aware Replacement Policy for NUMA Systems.
J. Inf. Sci. Eng., 2002

An Effective L2 Cache Replacement Policy to Distribute the Bus Traffic in the SMP Node.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Analysis of System Performance by Changing the Ring Architecture on the Dual Ring CC-NUMA System.
Proceedings of the 9th International Conference on Parallel and Distributed Systems, 2002

2001
Efficient schemes to scale the interconnection network bandwidth in a ring-based multiprocessor system.
Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001

Accelerating the Continuous Data in a SCI-Based Multimedia System.
Proceedings of the Eigth International Conference on Parallel and Distributed Systems, 2001

2000
Improving the Execution Efficiency of Barrier Synchronization in Software DSM through Static Analysis.
Int. J. High Speed Comput., 2000

Alternatives to Enhance the Performance of Disk I/O in Ring-Based Multiprocessors.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A Method for an Integrated Simulation Linked with Scheduling Policies on a Program-Driven Simulator.
Proceedings of the MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August, 2000

Analysis of slotted ring network in real-time systems.
Proceedings of the ISCA 15th International Conference Computers and Their Applications, 2000

1999
Optimal Interconnection Network Bandwidth for Ring-Based Multiprocessor Systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1998
Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing.
VLSI Design, 1998

Relaxed Barrier Synchronization for the BSP Model of Computation on Message-Passing Architectures.
Inf. Process. Lett., 1998

Reducing Coherence Overhead of Barrier Synchronization in Software DSMs.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1998

Efficient Barrier Synchronization Mechanism for BSP Model on Message Passing Architectures.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

PANDA: Ring-Based Multiprocessor System Using New Snooping Protocol.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998

1997
Reducing Overheads of Local Communications in Fine-grain Parallel Computation.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Quantitative Analysis on Caching Effect of I-Structure Data in Frame-Based Multithreaded Processing.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Hardware Support for Release Consistency with Queue-based Synchronization.
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

1996
COP: a Crosstalk OPtimizer for gridded channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A New FPGA Technology Mapping Approach by Cluster Merging.
Proceedings of the Field-Programmable Logic, 1996

1995
An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis.
IEICE Trans. Inf. Syst., 1995

Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Direct Synthesis of Efficient Speed-Independent Circuits from Deterministic Signal Transition Graphs.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1992
G-system: A Functionally-Based Communication System Model for Parallel Processing.
Proceedings of the Algorithms, Software, Architecture, 1992

1990
Functional C: an extended functional programming language.
Proceedings of the Next Decade in Information Technology: Proceedings of the 5th Jerusalem Conference on Information Technology 1990, 1990


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