Hyunbae Lee
According to our database1,
Hyunbae Lee
authored at least 8 papers
between 2004 and 2020.
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Bibliography
2020
All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector.
IEICE Electron. Express, 2020
A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction Logic.
Proceedings of the International SoC Design Conference, 2020
2016
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel.
IEEE J. Solid State Circuits, 2015
2014
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2014
A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2004
Level 1 & Victim Cache Management with Processor Reuse Information.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004