Chung-Bin Wu
Orcid: 0000-0001-6585-980X
According to our database1,
Chung-Bin Wu
authored at least 23 papers
between 2003 and 2023.
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Bibliography
2023
System Integration and Optimization of AI Hardware Acceleration Architecture for Object Detection.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023
2022
Design and FPGA Implementation of Lite Convolutional Neural Network Based Hardware Accelerator for Ocular Biometrics Recognition Technology.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
Hetero Layer Fusion Based Architecture Design and Implementation for of Deep Learning Accelerator.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
Quantized Lite Convolutional Neural Network Hardware Accelerator Design with FPGA for Face Direction Recognition.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Reconfigurable Deep Learning Accelerator Hardware Architecture Design for Sparse CNN.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
iAMEC, an Intelligent Autonomous Mover for Navigation in Indoor People Rich Environments.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020
Reconfigurable Hardware Architecture Design and Implementation for AI Deep Learning Accelerator.
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020
2019
IEEE Trans. Circuits Syst. Video Technol., 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019
2017
IEEE Trans. Consumer Electron., 2017
2016
A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC.
J. Signal Process. Syst., 2016
2015
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2012
A hardware sharing architecture of deblocking filter for VP8 and H.264/AVC video coding.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
An efficient background extraction and object segmentation algorithm for realtime applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2005
IEEE Trans. Circuits Syst. Video Technol., 2005
2003
A fuzzy-based impulse noise detection and cancellation for real-time processing in video receivers.
IEEE Trans. Instrum. Meas., 2003
IEEE Trans. Circuits Syst. Video Technol., 2003