Chunsheng Liu

According to our database, Chunsheng Liu authored at least 19 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives.

Fei Su, Chunsheng Liu, Haralampos-G. Stratigopoulos

IEEE Des. Test, April, 2023

Special Issue on Testability and Dependability of Artificial Intelligence Hardware.

Fei Su, Chunsheng Liu, Haralampos-G. Stratigopoulos

IEEE Des. Test, April, 2023

2022

C-Testing and Efficient Fault Localization for AI Accelerators.

Arjun Chaudhuri, Chunsheng Liu, Xiaoxin Fan, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020

C-Testing of AI Accelerators ^*.

Arjun Chaudhuri, Chunsheng Liu, Xiaoxin Fan, Krishnendu Chakrabarty

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2006

Constraint-Driven Test Scheduling for NoC-Based Systems.

Érika F. Cota, Chunsheng Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.

Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Reuse-based test access and integrated test scheduling for network-on-chip.

Chunsheng Liu, Zach Link, Dhiraj K. Pradhan

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Design and analysis of compact dictionaries for diagnosis in scan-BIST.

Chunsheng Liu, Krishnendu Chakrabarty

IEEE Trans. Very Large Scale Integr. Syst., 2005

EBIST: a novel test generator with built-in fault detection capability.

Dhiraj K. Pradhan, Chunsheng Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.

Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004

Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip.

Chunsheng Liu, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Compact Dictionaries for Fault Diagnosis in Scan-BIST.

Chunsheng Liu, Krishnendu Chakrabarty

IEEE Trans. Computers, 2004

Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.

Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.

Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003

Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment.

Chunsheng Liu, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Compact Dictionaries for Fault Diagnosis in BIST.

Chunsheng Liu, Krishnendu Chakrabarty

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

EBIST: A Novel Test Generator with Built-In Fault Detection Capability.

Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty

Proceedings of the 2003 Design, 2003

A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis.

Chunsheng Liu, Krishnendu Chakrabarty

Proceedings of the 2003 Design, 2003

2002

An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment.

Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel

Proceedings of the 2002 Design, 2002