Claude Arm

According to our database1, Claude Arm authored at least 12 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2019
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2016
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2010
A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core.
IEEE J. Solid State Circuits, 2009

An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core.
Proceedings of the ESSCIRC 2008, 2008

2006

2001
Low-power low-voltage library cells and memories.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Double-Latch Clocking Scheme for Low-Power I.P. Cores.
Proceedings of the Integrated Circuit Design, 2000

1997
Low-power design of 8-b embedded CoolRisc microcontroller cores.
IEEE J. Solid State Circuits, 1997

1996
Low-Power Embedded Microprocessor Design.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

1994
An 8-bit multitask micropower RISC core.
IEEE J. Solid State Circuits, August, 1994


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