D. Bradley

According to our database, D. Bradley authored at least 3 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology.

M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew, A. Chatterjee, B. Chauhan, N. Dandeti, J. Desai, M. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack, Y. Greenzweig, John Giacobbe, Walid M. Hafez, E. Haralson, A. Hegde, A. Illa, M. Islam, S. Jain, M. Jang, J. Nguyen, T. Tong, L. Jiang, Eric Karl, P. Kalangi, G. Khoo, A. Krishnamoorthy, B. Kuns, W. Li, R. Livengood, T. Malik, R. Priyanka, H. Faraby, Y. Maymon, K. Mistry, K. Morgan, S. Natarajan, O. Nevo, M. Oh, P. Pardy, J. Park, P. Penmatsa, Boyd Phelps, C. Peterson, S. Rajappa, A. Raveh, A Rezaie, T. Ravishankar, R. Ramaswamy, S. Reddy, R. Saha, S. Sen, R. Sanchez, R. Sanaga, B. Simkhovich, Bernhard Sell, M. Senger, B. Schnarch, M. Seshadri, O. Sidorov, S. Subramanian, K. Subramanian, B. Truong, S. Bangalore, Jeffery Hicks, S. Venkatesh, D. Christensen, K. Bhargav, M. Von Haartman, P. Joshi, S. Zickel, C.-H. Lin, J. Huening, T.-H. Wu, N. Bakken, A. Afzal, A. Raman, Sj. Rao, V. Kawar, J. Neirynck, D. Bradley, M. Duwe, S. Wu, V. Patil, M. Bayoumy

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2016

Design, modelling, simulation and integration of cyber physical systems: Methods and applications.

Peter Hehenberger, Birgit Vogel-Heuser, D. Bradley, Benoît Eynard, Tetsuo Tomiyama, Sofiane Achiche

Comput. Ind., 2016

2005

Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.

Tom Beacom, Timothy C. Buchholtz, D. Bradley, Jack Randolph, Salvatore N. Storino, Mark Veldhuizen, Sherman M. Dance, Jente B. Kuang, Steve Schwinn, Sue Cox, Fred Ziegler, J. Kao, Chuck Li, Christophe Tretz, J. Cabellon, Andrew Freemyer, Matthew Tubbs

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005