Jente B. Kuang

According to our database, Jente B. Kuang authored at least 17 papers between 2004 and 2015.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2015

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.

Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2013

Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology.

Xingsheng Wang, Binjie Cheng, Jente B. Kuang, Andrew R. Brown, Campbell Millar, Asen Asenov

IEEE Des. Test, 2013

SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.

Binjie Cheng, Xingsheng Wang, Andrew R. Brown, Jente B. Kuang, Dave Reid, Campbell Millar, Sani R. Nassif, Asen Asenov

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.

Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Jente B. Kuang, Sani R. Nassif, Asen Asenov

Proceedings of the European Solid-State Device Research Conference, 2013

2011

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.

Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

A 32nm 0.5V-supply dual-read 6T SRAM.

Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2009

Statistical yield analysis of silicon-on-insulator embedded DRAM.

Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.

Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka

IEEE Trans. Very Large Scale Integr. Syst., 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.

Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.

Jente B. Kuang, A. Mathews, J. Barth, Fadi H. Gebara, T. Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, E. Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata

Proceedings of the ESSCIRC 2008, 2008

2007

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.

Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

SRAM Local Bit Line Access Failure Analyses.

Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.

Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.

Tom Beacom, Timothy C. Buchholtz, D. Bradley, Jack Randolph, Salvatore N. Storino, Mark Veldhuizen, Sherman M. Dance, Jente B. Kuang, Steve Schwinn, Sue Cox, Fred Ziegler, J. Kao, Chuck Li, Christophe Tretz, J. Cabellon, Andrew Freemyer, Matthew Tubbs

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits.

Jente B. Kuang, Ching-Te Chuang

IEEE Trans. Circuits Syst. II Express Briefs, 2004

A low latency and low power dynamic Carry Save Adder.

Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004