Jente B. Kuang

According to our database1, Jente B. Kuang authored at least 17 papers between 2004 and 2015.

Collaborative distances:



In proceedings 
PhD thesis 




TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology.
IEEE Des. Test, 2013

SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.
Proceedings of the European Solid-State Device Research Conference, 2013

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011


A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

Statistical yield analysis of silicon-on-insulator embedded DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.
Proceedings of the ESSCIRC 2008, 2008

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

SRAM Local Bit Line Access Failure Analyses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A low latency and low power dynamic Carry Save Adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004