Daero Kim

According to our database, Daero Kim authored at least 6 papers between 2017 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

37.3 A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE.

Yoonjae Choi, Daero Kim, Myunggon Kim, Sangmin Lee, Hansol Kang, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Cho, Boyoung Kang, Kyoungwon Lee, Jaegeun Song, Jinho Choi, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Hyo-Gyuem Rhew

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2024

Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers.

Jaeyoon Lee, Wonyeong Jung, Dongwhee Kim, Daero Kim, Junseung Lee, Jungrae Kim

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM.

Yoonjae Choi, Jaegeun Song, Daero Kim, Myunggon Kim, Jiyeon Park, Jinho Choi, Changki Kwon, Minho Seo, Jihun Oh, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Jongshin Shin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

Carbon-Aware and Fault-Tolerant Migration of Deep Learning Workloads in the Geo-Distributed Cloud.

Jeonghyeon Park, Daero Kim, Jiseon Kim, Jungkyu Han, Sejin Chun

Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024

2022

Adaptive Granularity On-die ECC.

Daero Kim, Jungrae Kim

Proceedings of the 19th International SoC Design Conference, 2022

2017

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller.

Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017