Dariusz Czysz

According to our database1, Dariusz Czysz authored at least 14 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Perspectives of Motor Functional Upper Extremity Recovery with the Use of Immersive Virtual Reality in Stroke Patients.
Sensors, January, 2023

2013
On Deploying Scan Chains for Data Storage in Test Compression Environment.
IEEE Des. Test, 2013

2012
Low power test application with selective compaction in VLSI designs.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Reduced ATE Interface for High Test Data Compression.
Proceedings of the 16th European Test Symposium, 2011

2010
On Compaction Utilizing Inter and Intra-Correlation of Unknown States.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Low power compression of incompatible test cubes.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Low-Power Scan Operation in Test Compression Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Highly X-Tolerant Selective Compaction of Test Responses.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Compression based on deterministic vector clustering of incompatible test cubes.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low Power Scan Shift and Capture in the EDT Environment.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Low Power Embedded Deterministic Test.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

New Test Data Decompressor for Low Power Applications.
Proceedings of the 44th Design Automation Conference, 2007


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