Grzegorz Mrugalski

Orcid: 0000-0001-9378-127X

According to our database1, Grzegorz Mrugalski authored at least 65 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
X-Masking for Deterministic In-System Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

2022
LBIST for Automotive ICs With Enhanced Test Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DIST: Deterministic In-System Test with X-masking.
Proceedings of the IEEE International Test Conference, 2022

X-Masking for In-System Deterministic Test.
Proceedings of the IEEE European Test Symposium, 2022

2021
X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Autonomous Scan Patterns for Laser Voltage Imaging.
IEEE Trans. Emerg. Top. Comput., 2021

2020
Scan Integrity Tests for EDT Compression.
IEEE Des. Test, 2020

X-Tolerant Tunable Compactor for In-System Test.
Proceedings of the IEEE International Test Conference, 2020

Test Sequence-Optimized BIST for Automotive Applications.
Proceedings of the IEEE European Test Symposium, 2020

Scan Chain Diagnosis-Driven Test Response Compactor.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
On Cyclic Scan Integrity Tests for EDT-based Compression.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2017
Trimodal Scan-Based Test Paradigm.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2015
Low-Power Programmable PRPG With Test Compression Capabilities.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A deterministic BIST scheme based on EDT-compressed test patterns.
Proceedings of the 2015 IEEE International Test Conference, 2015

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On Using Implied Values in EDT-based Test Compression.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Low Power Test Compression with Programmable Broadcast-Based Control.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Test Time Reduction in EDT Bandwidth Management for SoC Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On Deploying Scan Chains for Data Storage in Test Compression Environment.
IEEE Des. Test, 2013

New test compression scheme based on low power BIST.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
EDT Bandwidth Management in SoC Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Test generator with preselected toggling for low power built-in self-test.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low power programmable PRPG with enhanced fault coverage gradient.
Proceedings of the 2012 IEEE International Test Conference, 2012

Bandwidth-aware test compression logic for SoC designs.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs.
J. Electron. Test., 2011

Ring Generator: An Ultimate Linear Feedback Shift Register.
Computer, 2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.
Proceedings of the 2011 IEEE International Test Conference, 2011

Reduced ATE Interface for High Test Data Compression.
Proceedings of the 16th European Test Symposium, 2011

Diagnosis of Failing Scan Cells through Orthogonal Response Compaction.
Proceedings of the 16th European Test Symposium, 2011

Fault Diagnosis in Memory BIST Environment with Non-march Tests.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Low Power Decompressor and PRPG with Constant Value Broadcast.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
On Compaction Utilizing Inter and Intra-Correlation of Unknown States.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Dynamic channel allocation for higher EDT compression in SoC designs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Low power compression of incompatible test cubes.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Low-Power Scan Operation in Test Compression Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Highly X-Tolerant Selective Compaction of Test Responses.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Compression based on deterministic vector clustering of incompatible test cubes.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low Power Scan Shift and Capture in the EDT Environment.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Fault Diagnosis With Convolutional Compactors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Isolation of Failing Scan Cells through Convolutional Test Response Compaction.
J. Electron. Test., 2007

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.
IEEE Des. Test Comput., 2007

Low Power Embedded Deterministic Test.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

New Test Data Decompressor for Low Power Applications.
Proceedings of the 44th Design Automation Conference, 2007

2006
High Performance Dense Ring Generators.
IEEE Trans. Computers, 2006

X-Press Compactor for 1000x Reduction of Test Data.
Proceedings of the 2006 IEEE International Test Conference, 2006

Test response compactor with programmable selector.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Diagnosis with convolutional compactors in presence of unknown states.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Convolutional compaction-driven diagnosis of scan failures.
Proceedings of the 10th European Test Symposium, 2005

2004
Ring generators - new devices for embedded test applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Planar High Performance Ring Generators.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Fault Diagnosis in Designs with Convolutional Compactors.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
2D Test Sequence Generators.
IEEE Des. Test Comput., 2003

High Speed Ring Generators and Compactors of Test Data.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002
Embedded Deterministic Test for Low-Cost Manufacturing Test.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000
Cellular automata-based test pattern generators with phase shifters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Synthesis of pattern generators based on cellular automata with phase shifters.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999


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