Farhana Sheikh

Orcid: 0000-0001-5078-0816

According to our database1, Farhana Sheikh authored at least 45 papers between 2002 and 2023.

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Bibliography

2023
Guest Editorial 2022 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, March, 2023

Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Open-Source AXI4 Adapters for Chiplet Architectures.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Comparative Performance of 100-200 GHz Wideband Transceivers: CMOS vs Compound Semiconductors.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023

2022
Guest Editorial: Special Issue on Advances in Signal Processing Systems.
J. Signal Process. Syst., 2022

Guest Editorial 2021 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2022

2021
Editorial on the Special Section on Algorithms, Circuits, and Systems for Signal Processing at the Edge.
IEEE Open J. Circuits Syst., 2021

A 1070 pJ/b 169 Mb/s Quad-core Digital Baseband SoC for Distributed and Cooperative Massive MIMO in 28 nm FD-SOI.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021


A 16mm<sup>2</sup> 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons.
IEEE J. Solid State Circuits, 2020

19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Low-Complexity Fully-Digital Phase Noise Suppression for Millimeter-Wave Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Multi-die Integration Using Advanced Packaging Technologies.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Phase Noise Compensation for OFDM Systems Exploiting Coherence Bandwidth.
Proceedings of the 20th IEEE International Workshop on Signal Processing Advances in Wireless Communications, 2019

A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

EE2: Workshop on circuits for social good.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


Impact of Relay Cooperation on the Performance of Large-Scale Multipair Two-Way Relay Networks.
Proceedings of the IEEE Global Communications Conference, 2018

2017
Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

Guest Editorial Advanced Baseband Processing Circuits and Systems for 5G Communications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

Adaptive and multi-mode baseband systems for next generation wireless communication.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication.
J. Signal Process. Syst., 2016

High-throughput lattice reduction for large-scale MIMO systems based on Seysen's algorithm.
Proceedings of the 2016 IEEE International Conference on Communications, 2016

2015
Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

2014
Channel-adaptive complex K-best MIMO detection using lattice reduction.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

2013
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS.
IEEE J. Solid State Circuits, 2013

A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2013

2012
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors.
IEEE J. Solid State Circuits, 2012

A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
53 Gbps Native GF(2 <sup>4</sup>) <sup>2</sup> Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors.
IEEE J. Solid State Circuits, 2011

A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

High-performance energy-efficient encryption in the sub-45nm CMOS Era.
Proceedings of the 48th Design Automation Conference, 2011

2010
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2004
Level conversion for dual-supply systems.
IEEE Trans. Very Large Scale Integr. Syst., 2004

2002
Minimum-power retiming for dual-supply CMOS circuits.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002


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