Dina Kamel

Orcid: 0000-0002-7238-9567

According to our database1, Dina Kamel authored at least 16 papers between 2009 and 2022.

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Bibliography

2022
When Bad News Become Good News Towards Usable Instances of Learning with Physical Errors.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

2021
Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Side-channel analysis of a learning parity with physical noise processor.
J. Cryptogr. Eng., 2021

2020
Learning with Physical Noise or Errors.
IEEE Trans. Dependable Secur. Comput., 2020

2018
Demonstrating an LPPN Processor.
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018

2017
Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

2016
Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

2015
Side-channel attacks from static power: when should we care?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Understanding the limitations and improving the relevance of SPICE simulations in side-channel security evaluations.
J. Cryptogr. Eng., 2014

2013
Strong PUFs and their (physical) unpredictability: a case study with power PUFs.
Proceedings of the Workshop on Embedded Systems Security, 2013

2011
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags.
J. Cryptogr. Eng., 2011

A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices.
Proceedings of the Advances in Cryptology - EUROCRYPT 2011, 2011

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010
Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Scaling Trends of the AES S-box Low Power Consumption in 130 and 65 nm CMOS Technology Nodes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009


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