Diwesh Pandey

Orcid: 0000-0002-3905-2014

According to our database1, Diwesh Pandey authored at least 4 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

LEO: Line End Optimizer for Sub-7nm Technology Nodes.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2020
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2015
Virtual logic netlist: Enabling efficient RTL analysis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015


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