Gustavo E. Téllez

According to our database, Gustavo E. Téllez authored at least 21 papers between 1994 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

LEO: Line End Optimizer for Sub-7nm Technology Nodes.

Diwesh Pandey, Gustavo E. Téllez, James Leland

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2020

Self-Aligned Double-Patterning Aware Legalization.

Hua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Latch Clustering for Timing-Power Co-Optimization.

Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques.

Alexey Lvov, Gustavo E. Téllez, Gi-Joon Nam

Proceedings of the 2018 International Symposium on Physical Design, 2018

Interconnect Optimization Considering Multiple Critical Paths.

Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam

Proceedings of the 2018 International Symposium on Physical Design, 2018

2015

Detailed Routing Algorithms for Advanced Technology Nodes.

Markus Ahrens, Michael Gester, Niko Klewinghaus, Dirk Müller, Sven Peyer, Christian Schulte, Gustavo E. Téllez

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Techniques for scalable and effective routability evaluation.

Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar

ACM Trans. Design Autom. Electr. Syst., 2014

2012

GLARE: global and local wiring aware routability evaluation.

Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Design methodology for the IBM POWER7 microprocessor.

Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez

IBM J. Res. Dev., 2011

2010

What makes a design difficult to route.

Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez

Proceedings of the 2010 International Symposium on Physical Design, 2010

2001

Activity-driven clock design.

Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000

EDA in IBM: past, present, and future.

John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1998

On Rectilinear Distance-Preserving Trees.

Gustavo E. Téllez, Majid Sarrafzadeh

VLSI Design, 1998

Exploiting Sleep Mode for Memory Partitioning and Other Applications.

Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh

VLSI Design, 1998

1997

Minimal buffer insertion in clock trees with skew and slew rate constraints.

Gustavo E. Téllez, Majid Sarrafzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A delay budgeting algorithm ensuring maximum flexibility in placement.

Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation.

Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez

Proceedings of the 1997 International Symposium on Physical Design, 1997

Unification of Budgeting and Placement.

Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez

Proceedings of the 34st Conference on Design Automation, 1997

1995

Activity-driven clock design for low power circuits.

Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Memory Segmentation to Exploit Sleep Mode Operation.

Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh

Proceedings of the 32st Conference on Design Automation, 1995

1994

Clock period constrained minimal buffer insertion in clock trees.

Gustavo E. Téllez, Majid Sarrafzadeh

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994