Lakshmi N. Reddy

According to our database1, Lakshmi N. Reddy authored at least 22 papers between 1991 and 2020.

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Bibliography

2020
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2018
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Interconnect Optimization Considering Multiple Critical Paths.
Proceedings of the 2018 International Symposium on Physical Design, 2018

2016
Gate movement for timing improvement on row based Dual-VDD designs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

OWARU: free space-aware timing-driven incremental placement.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2014
Techniques for scalable and effective routability evaluation.
ACM Trans. Design Autom. Electr. Syst., 2014

2013
Depth controlled symmetric function fanin tree restructure.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Intuitive ECO synthesis for high performance circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
GLARE: global and local wiring aware routability evaluation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev., 2011

2010
Logical and physical restructuring of fan-in trees.
Proceedings of the 2010 International Symposium on Physical Design, 2010

2008
Placement-Driven Synthesis Design Closure Tool.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

2004
An Integrated Environment for Technology Closure of Deep-Submicron IC Designs.
IEEE Des. Test Comput., 2004

2000
Transformational Placement and Synthesis.
Proceedings of the 2000 Design, 2000

1999
Performance Driven Optimization of Network Length in Physical Placement.
Proceedings of the IEEE International Conference On Computer Design, 1999

1996
BooleDozer: Logic synthesis for ASICs.
IBM J. Res. Dev., 1996

1993
COMPACTEST: a method to generate compact test sets for combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
A Small Test Generator for Large Designs.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

SPADES: a simulator for path delay faults in sequential circuits.
Proceedings of the conference on European design automation, 1992

1991
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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