Arun Joseph

According to our database1, Arun Joseph authored at least 18 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
An evaluation of methods to port legacy code to SGX enclaves.
Proceedings of the ESEC/FSE '20: 28th ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering, 2020

2019
Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management.
ACM J. Emerg. Technol. Comput. Syst., 2019

Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors.
IET Comput. Digit. Tech., 2019

Dynamic simulation of the reverse osmosis process for seawater using LabVIEW and an analysis of the process performance.
Comput. Chem. Eng., 2019

Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018
Fast Secure Computation for Small Population over the Internet.
IACR Cryptol. ePrint Arch., 2018

Economic outage scheduling of transmission line for long-term horizon under demand and wind scenarios.
Proceedings of the 2018 IEEE PES Innovative Smart Grid Technologies Conference Europe, 2018

Predictive Mitigation of Short Term Voltage Instability Using a Faster Than Real-Time Digital Replica.
Proceedings of the 2018 IEEE PES Innovative Smart Grid Technologies Conference Europe, 2018

Prediction of Short-Term Voltage Instability Using a Digital Faster than Real-Time Replica.
Proceedings of the IECON 2018, 2018

2016
Low cost ultra-pure sine wave generation with self calibration.
Proceedings of the 2016 IEEE International Test Conference, 2016

FVCAG: A framework for formal verification driven power modeling and verification.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015
FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware.
Proceedings of the 28th International Conference on VLSI Design, 2015

Virtual logic netlist: Enabling efficient RTL analysis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

FreqLeak: A frequency step based method for efficient leakage power characterization in a system.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
Process Synchronization in Multi-core Systems Using On-Chip Memories.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Empirically derived abstractions in uncore power modeling for a server-class processor chip.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Sound localization and Visualization device.
Proceedings of the 2013 IEEE Global Humanitarian Technology Conference, 2013


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