Peeter Ellervee

Orcid: 0000-0002-0745-6743

According to our database1, Peeter Ellervee authored at least 52 papers between 1994 and 2023.

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Bibliography

2023
ML-Based Online Design Error Localization for RISC-V Implementations.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

2022
Surviving the Unforeseen - Teaching IT and Engineering Students During COVID-19 Outbreak.
Proceedings of the IEEE Frontiers in Education Conference, 2022

2021
JÄNES: A NAS Framework for ML-based EDA Applications.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
Wafer-Level Die Re-Test Success Prediction Using Machine Learning.
Proceedings of the IEEE Latin-American Test Symposium, 2020

SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2017
Guest Editorial: Implementation Issues in System-on-Chip.
J. Signal Process. Syst., 2017

Performance estimation of embedded applications on microcontrollers.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Standards-based tools and services for building lifelong learning pathways.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

2016
Polymorphic Configuration Architecture for CGRAs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

SoCDep<sup>2</sup>: A framework for dependable task deployment on many-core systems under mixed-criticality constraints.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Data type dependent energy consumption estimation.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2015
Functional self-test of high-performance pipe-lined signal processing architectures.
Microprocess. Microsystems, 2015

DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs.
Proceedings of the 28th International Conference on VLSI Design, 2015

Microcontroller energy consumption estimation based on software analysis for embedded systems.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Digital system modeling and synthesis as an introduction to Computer Systems Engineering.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

Flexible controller for educational robot kit.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

An ad-hoc implementation of a remote laboratory.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

2014
Optimization of multisine excitation for a bioimpedance measurement device.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

Customizable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Hardware close programming for freshmen.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Morphable Compression Architecture for Efficient Configuration in CGRAs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Guest Editorial.
Microprocess. Microsystems, 2013

At-speed self-testing of high-performance pipe-lined processing architectures.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

2012
Multisine signal generation method for a bioimpedance measurement device.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Contention aware scheduling for NoC-based real-time systems.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Experience in increase of practical hours for HDL course.
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

EEG Analyzer prototype based on FPGA.
Proceedings of the 7th International Symposium on Image and Signal Processing and Analysis, 2011

Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Communication modelling and synthesis for NoC-based systems with real-time constraints.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Guest Editorial.
Microprocess. Microsystems, 2010

2009
Scheduling framework for real-time dependable NoC-based systems.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

2008
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Code Coverage Analysis using High-Level Decision Diagrams.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
FPGA-based fault emulation of synchronous sequential circuits.
IET Comput. Digit. Tech., 2007

HDL-s for Students with Different Background.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006
Work in Progress: FPGA Based Emulation Environment.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

2005
Improved Fault Emulation for Synchronous Sequential Circuits.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Evaluating Fault Emulation on FPGA.
Proceedings of the Field Programmable Logic and Application, 2004

2002
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001
System-level data-format exploration for dynamically allocated datastructures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Digital Hardware Organization Course for SoC Program.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

2000
TOP: An Algorithm for Three-Level Optimization of PLDs.
Proceedings of the 2000 Design, 2000

System-level data format exploration for dynamically allocated data structures.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Globally asynchronous locally synchronous architecture for large high-performance ASICs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Exploiting Data Transfer Locality in Memory Mapping.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Revolver: A High-Performance MIMD Architecture for Collision Free Computing.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1996
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1994
Hardware/software partitioning and minimizing memory interface traffic.
Proceedings of the Proceedings EURO-DAC'94, 1994


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