Dominik Erb

According to our database1, Dominik Erb authored at least 20 papers between 2013 and 2018.

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Bibliography

2018
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Characterization of possibly detected faults by accurately computing their detection probability.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG.
J. Electron. Test., 2017

Efficient SAT-based generation of hazard-activated TSOF tests.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Evaluating the effectiveness of D-chains in SAT-based ATPG.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
On the handling of uncertainty in test pattern generation.
PhD thesis, 2016

Applying Tailored Formal Methods to X-ATPG.
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016

Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Improving test pattern generation in presence of unknown values beyond restricted symbolic logic.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Exact Logic and Fault Simulation in Presence of Unknowns.
ACM Trans. Design Autom. Electr. Syst., 2014

Test pattern generation in presence of unknown values based on restricted symbolic logic.
Proceedings of the 2014 International Test Conference, 2014

Efficient SMT-based ATPG for interconnect open defects.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Accurate QBF-based test pattern generation in presence of unknown values.
Proceedings of the Design, Automation and Test in Europe, 2013

Accurate Multi-cycle ATPG in Presence of X-Values.
Proceedings of the 22nd Asian Test Symposium, 2013


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