According to our database1, Anant Singh authored at least 7 papers between 2009 and 2020.
Legend:Book In proceedings Article PhD thesis Other
IEEE J. Solid State Circuits, 2020
Physical Insights into Phosphorene Transistor Degradation Under Exposure to Atmospheric Conditions and Electrical Stress.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE International Solid-State Circuits Conference, 2009