Dong-Ryeol Oh

Orcid: 0000-0002-5454-5191

According to our database1, Dong-Ryeol Oh authored at least 10 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC.
IEEE J. Solid State Circuits, August, 2024

2022
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique.
IEEE J. Solid State Circuits, 2022

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021

2020
A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC.
IEEE Trans. Circuits Syst., 2020

An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration.
IEEE J. Solid State Circuits, 2019

2015
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation.
IEEE J. Solid State Circuits, 2015

A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

2008
Real-Time Point-Based Rendering Using Visibility Map.
IEICE Trans. Inf. Syst., 2008


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