Doosan Cho

Orcid: 0000-0002-1681-432X

According to our database¹, Doosan Cho authored at least 19 papers between 2006 and 2019.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2019

A spill data aware memory assignment technique for improving power consumption of multimedia memory systems.

[BibT_eX]

[DOI]

Jonghee M. Youn

Doosan Cho

Multim. Tools Appl., 2019

2018

A Prediction Method of Solar Power Generator using Machine Learning Techniques.

[BibT_eX]

[DOI]

Jungseok Cho

Jeongdoo Lee

Doosan Cho

Proceedings of the Parallel and Distributed Computing, 2018

2017

Improving memory system performance for multimedia applications.

[BibT_eX]

[DOI]

Jonghee M. Youn

Doosan Cho

Multim. Tools Appl., 2017

2015

Energy Consumption Reduction Technique on Smart Devices for Communication-Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Science and Ubiquitous Computing, 2015

2013

Architecture customization of on-chip reconfigurable accelerators.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Reducing instruction bit-width for low-power VLIW architectures.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

2012

A Delay and Distance Aware Code Mapping Technique for Coarse-Grained Reconfigurable Array Processors.

[BibT_eX]

[DOI]

Jonghee M. Youn

Doosan Cho

Proceedings of the Convergence and Hybrid Information Technology, 2012

An Efficient Application Mapping for Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the Convergence and Hybrid Information Technology, 2012

An Efficient Management Technique for Fast SRAM Subsystems.

[BibT_eX]

[DOI]

Jongwon Lee

Doosan Cho

Yunheung Paek

Proceedings of the Convergence and Hybrid Information Technology, 2012

2011

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Memory Access Pattern Based Data Distribution Technique for Array Processors.

[BibT_eX]

[DOI]

Doosan Cho

Proceedings of the Convergence and Hybrid Information Technology, 2011

I<sup>2</sup>CRF: Incremental interconnect customization for embedded reconfigurable fabrics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2009

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Iterative Algorithm for Compound Instruction Selection with Register Coalescing.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Compiler driven data layout optimization for regular/irregular array access patterns.

[BibT_eX]

[DOI]

Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

2007

Efficient embedded code generation with multiple load/store instructions.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2007

Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors.

[BibT_eX]

[DOI]

Proceedings of the Compiler Construction, 16th International Conference, 2007

Software controlled memory layout reorganization for irregular array access patterns.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Compilers, 2007

2006

Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.

[BibT_eX]

[DOI]

Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2006

Doosan Cho

Timeline

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