Minwook Ahn

According to our database1, Minwook Ahn authored at least 25 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Online Speech Dereverberation Using RLS-WPE Based on a Full Spatial Correlation Matrix Integrated in a Speech Enhancement System.
Proceedings of the 16th International Workshop on Acoustic Signal Enhancement, 2018

2015
Source level offloading for special-purpose hardware accelerators.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

2014
JTS-based static branch prediction.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Nop compression scheme for high speed DSPs based on VLIW architecture.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

2013
The acceleration of various multimedia applications on reconfigurable processor.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Reevaluating the latency claims of 3D stacked memories.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Verification of CGRA Executable Code and Debugging of Memory Dependence Violation.
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

SCC based modulo scheduling for coarse-grained reconfigurable processors.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2010
Two versions of architectures for dynamic implied addressing mode.
J. Syst. Archit., 2010

2009
A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.
Trans. High Perform. Embed. Archit. Compil., 2009

Register coalescing techniques for heterogeneous register architecture with copy sifting.
ACM Trans. Embed. Comput. Syst., 2009

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A new addressing mode for the encoding space problem on embedded processors.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Orthogonal Instruction Encoding for a 16-bit Embedded Processor with Dynamic Implied Addressing Mode.
Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications, 2009

Iterative Algorithm for Compound Instruction Selection with Register Coalescing.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Efficient embedded code generation with multiple load/store instructions.
Softw. Pract. Exp., 2007

Optimistic coalescing for heterogeneous register architectures.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

2006
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2003
Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003


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