Jongeun Lee

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Specializing CGRAs for Light-Weight Convolutional Neural Networks.

[BibT_eX]

[DOI]

Jungi Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Diagnosis-informed connectivity subtyping discovers subgroups of autism with reproducible symptom profiles.

[BibT_eX]

[DOI]

NeuroImage, 2022

Accurate Prediction of ReRAM Crossbar Performance Under I-V Nonlinearity and IR Drop.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Squeezing Accumulators in Binary Neural Networks for Extremely Resource-Constrained Applications.

[BibT_eX]

[DOI]

Azat Azamat

Jaewoo Park

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Non-uniform Step Size Quantization for Accurate Post-training Quantization.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2022, 2022

An Empirical Study on How People Perceive AI-generated Music.

[BibT_eX]

[DOI]

Proceedings of the 31st ACM International Conference on Information & Knowledge Management, 2022

Centered Symmetric Quantization for Hardware-Efficient Low-Bit Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 33rd British Machine Vision Conference 2022, 2022

Multi-Fidelity Nonideality Simulation and Evaluation Framework for Resistive Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022

2021

Fast and Low-Cost Mitigation of ReRAM Variability for Deep Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

Azat Azamat

Faaiz Asim

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks.

[BibT_eX]

[DOI]

Jungi Lee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Automated Log-Scale Quantization for Low-Cost Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

2020

CaseCrawler: A Lightweight and Low-Profile Crawling Phone Case Robot.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., 2020

RRNet: Repetition-Reduction Network for Energy Efficient Depth Estimation.

[BibT_eX]

[DOI]

IEEE Access, 2020

IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays.

[BibT_eX]

[DOI]

IEEE Access, 2020

SparTANN: sparse training accelerator for neural networks with threshold-based sparsification.

[BibT_eX]

[DOI]

Hyeonuk Sim

Jooyeon Choi

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Cost-effective stochastic MAC circuits for deep neural networks.

[BibT_eX]

[DOI]

Hyeonuk Sim

Neural Networks, 2019

RRNet: Repetition-Reduction Network for Energy Efficient Decoder of Depth Estimation.

[BibT_eX]

[DOI]

CoRR, 2019

Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Efficient FPGA implementation of local binary convolutional neural network.

[BibT_eX]

[DOI]

Aidyn Zhakatayev

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Log-quantized stochastic computing for memory and computation efficient DNNs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration.

[BibT_eX]

[DOI]

Jason Helge Anderson

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA.

[BibT_eX]

[DOI]

Daewoo Kim

Sugil Lee

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

FPGA Architecture Enhancements for Efficient BNN Implementation.

[BibT_eX]

[DOI]

Jin Hee Kim

Jason Helge Anderson

Proceedings of the International Conference on Field-Programmable Technology, 2018

Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

DPS: dynamic precision scaling for stochastic computing-based deep neural networks.

[BibT_eX]

[DOI]

Saken Kenzhegulov

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Sangyun Oh

Hongsik Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Bio-inspired Design of a Double-Sided Crawling Robot.

[BibT_eX]

[DOI]

Gwang-Pil Jung

Kyu-Jin Cho

Proceedings of the Biomimetic and Biohybrid Systems - 6th International Conference, 2017

Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

FPGA implementation of convolutional neural network based on stochastic computing.

[BibT_eX]

[DOI]

Daewoo Kim

Mansureh S. Moghaddam

Proceedings of the International Conference on Field Programmable Technology, 2017

Design space exploration of FPGA accelerators for convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs.

[BibT_eX]

[DOI]

Dong Nguyen

Daewoo Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Scalable stochastic-computing accelerator for convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces.

[BibT_eX]

[DOI]

Atul Rahman

IEEE Trans. Very Large Scale Integr. Syst., 2016

Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A new approach to binarizing neural networks.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array.

[BibT_eX]

[DOI]

Atul Rahman

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Communication-aware mapping of stream graphs for multi-GPU platforms.

[BibT_eX]

[DOI]

Dong Nguyen

Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

An energy-efficient random number generator for stochastic circuits.

[BibT_eX]

[DOI]

Kyounghoon Kim

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Optimizing stream program performance on CGRA-based systems.

[BibT_eX]

[DOI]

Hongsik Lee

Dong Nguyen

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Configurable range memory for effective data reuse on programmable accelerators.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

Design and optimization for embedded and real-time computing systems and applications.

[BibT_eX]

[DOI]

Steve Goddard

Chin-Fu Kuo

J. Syst. Archit., 2014

Improving performance of loops on DIAM-based VLIW architectures.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Efficient Software-Based Runtime Binary Translation for Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Toan X. Mai

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Flattening-based mapping of imperfect loop nests for CGRAs?

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013

Architecture customization of on-chip reconfigurable accelerators.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Software-based register file vulnerability reduction for embedded processors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Evaluator-executor transformation for efficient pipelining of loops with conditionals.

[BibT_eX]

[DOI]

Yeonghun Jeong

Seongseok Seo

ACM Trans. Archit. Code Optim., 2013

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs.

[BibT_eX]

[DOI]

Yeonghun Jeong

Sungsok Seo

Proceedings of the Design, Automation and Test in Europe, 2013

Compiling control-intensive loops for CGRAs with state-based full predication.

[BibT_eX]

[DOI]

Kyuseung Han

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Return Data Interleaving for Multi-Channel Embedded CMPs Systems.

[BibT_eX]

[DOI]

Fei Hong

IEEE Trans. Very Large Scale Integr. Syst., 2012

PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

Improving performance of nested loops on reconfigurable array processors.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2012

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Software-managed automatic data sharing for Coarse-Grained Reconfigurable coprocessors.

[BibT_eX]

[DOI]

Toan X. Mai

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Memory access optimization in compilation for coarse-grained reconfigurable architectures.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Static Analysis of Register File Vulnerability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fast graph-based instruction selection for multi-output instructions.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2011

CRM: Configurable Range Memory for Fast Reconfigurable Computing.

[BibT_eX]

[DOI]

Jong Kyung Paek

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

I<sup>2</sup>CRF: Incremental interconnect customization for embedded reconfigurable fabrics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Binary acceleration using coarse-grained reconfigurable architecture.

[BibT_eX]

[DOI]

Jong Kyung Paek

SIGARCH Comput. Archit. News, 2010

Cache vulnerability equations for protecting data in embedded processor caches from soft errors.

[BibT_eX]

[DOI]

Reiley Jeyapaul

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Operation and data mapping for CGRAs with multi-bank memory.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

2009

A Software-Only Solution to Use Scratch Pads for Stack Data.

[BibT_eX]

[DOI]

Arun Kannan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A compiler optimization to reduce soft errors in register files.

[BibT_eX]

[DOI]

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

FSAF: File system aware flash translation layer for NAND Flash Memories.

[BibT_eX]

[DOI]

Sai Krishna Mylavarapu

Proceedings of the Design, Automation and Test in Europe, 2009

Static analysis to mitigate soft errors in register files.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Compiler-managed register file protection for energy-efficient soft error reduction.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A software solution for dynamic stack management on scratch pad memory.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2008

SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2008

Static analysis of processor stall cycle aggregation.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Hanmadang: entertainment systems for massive face-to-face interaction.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Advances in Computer Entertainment Technology, 2008

2007

Instruction set synthesis with efficient instruction encoding for configurable processors.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

2004

Analysis on risk factors for cervical cancer using induction technique.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2004

2003

Compilation Approach for Coarse-Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

An algorithm for mapping loops onto coarse-grained reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 2003 Conference on Languages, 2003

Energy-efficient instruction set synthesis for application-specific processors.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002

Efficient instruction encoding for automatic instruction set design of configurable ASIPs.

[BibT_eX]

[DOI]