Jongeun Lee

According to our database1, Jongeun Lee authored at least 75 papers between 2000 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Cost-effective stochastic MAC circuits for deep neural networks.
Neural Networks, 2019

RRNet: Repetition-Reduction Network for Energy Efficient Decoder of Depth Estimation.
CoRR, 2019

Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Efficient FPGA implementation of local binary convolutional neural network.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Log-quantized stochastic computing for memory and computation efficient DNNs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework.
Proceedings of the 2018 International Symposium on Physical Design, 2018

FPGA Architecture Enhancements for Efficient BNN Implementation.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

DPS: dynamic precision scaling for stochastic computing-based deep neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

FPGA implementation of convolutional neural network based on stochastic computing.
Proceedings of the International Conference on Field Programmable Technology, 2017

Design space exploration of FPGA accelerators for convolutional neural networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Scalable stochastic-computing accelerator for convolutional neural networks.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces.
IEEE Trans. VLSI Syst., 2016

Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A new approach to binarizing neural networks.
Proceedings of the International SoC Design Conference, 2016

Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Communication-aware mapping of stream graphs for multi-GPU platforms.
Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

An energy-efficient random number generator for stochastic circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Optimizing stream program performance on CGRA-based systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Configurable range memory for effective data reuse on programmable accelerators.
ACM Trans. Design Autom. Electr. Syst., 2014

Design and optimization for embedded and real-time computing systems and applications.
Journal of Systems Architecture - Embedded Systems Design, 2014

Improving performance of loops on DIAM-based VLIW architectures.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Efficient Software-Based Runtime Binary Translation for Coarse-Grained Reconfigurable Architectures.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Flattening-based mapping of imperfect loop nests for CGRAs?
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013
Architecture customization of on-chip reconfigurable accelerators.
ACM Trans. Design Autom. Electr. Syst., 2013

Software-based register file vulnerability reduction for embedded processors.
ACM Trans. Embedded Comput. Syst., 2013

Evaluator-executor transformation for efficient pipelining of loops with conditionals.
TACO, 2013

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.
J. Solid-State Circuits, 2013

Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs.
Proceedings of the Design, Automation and Test in Europe, 2013

Compiling control-intensive loops for CGRAs with state-based full predication.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Return Data Interleaving for Multi-Channel Embedded CMPs Systems.
IEEE Trans. VLSI Syst., 2012

PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2012

Improving performance of nested loops on reconfigurable array processors.
TACO, 2012

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Software-managed automatic data sharing for Coarse-Grained Reconfigurable coprocessors.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Memory access optimization in compilation for coarse-grained reconfigurable architectures.
ACM Trans. Design Autom. Electr. Syst., 2011

Static Analysis of Register File Vulnerability.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Fast graph-based instruction selection for multi-output instructions.
Softw., Pract. Exper., 2011

CRM: Configurable Range Memory for Fast Reconfigurable Computing.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Binary acceleration using coarse-grained reconfigurable architecture.
SIGARCH Computer Architecture News, 2010

Cache vulnerability equations for protecting data in embedded processor caches from soft errors.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Operation and data mapping for CGRAs with multi-bank memory.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

2009
A Software-Only Solution to Use Scratch Pads for Stack Data.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A compiler optimization to reduce soft errors in register files.
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

FSAF: File system aware flash translation layer for NAND Flash Memories.
Proceedings of the Design, Automation and Test in Europe, 2009

Static analysis to mitigate soft errors in register files.
Proceedings of the Design, Automation and Test in Europe, 2009

Compiler-managed register file protection for energy-efficient soft error reduction.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A software solution for dynamic stack management on scratch pad memory.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures.
IJES, 2008

SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories.
Proceedings of the High Performance Computing, 2008

Static analysis of processor stall cycle aggregation.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Hanmadang: entertainment systems for massive face-to-face interaction.
Proceedings of the International Conference on Advances in Computer Entertainment Technology, 2008

2007
Instruction set synthesis with efficient instruction encoding for configurable processors.
ACM Trans. Design Autom. Electr. Syst., 2007

2004
Analysis on risk factors for cervical cancer using induction technique.
Expert Syst. Appl., 2004

2003
Compilation Approach for Coarse-Grained Reconfigurable Architectures.
IEEE Design & Test of Computers, 2003

An algorithm for mapping loops onto coarse-grained reconfigurable architectures.
Proceedings of the 2003 Conference on Languages, 2003

Energy-efficient instruction set synthesis for application-specific processors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Efficient instruction encoding for automatic instruction set design of configurable ASIPs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2000
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor.
Proceedings of the 2000 Design, 2000


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