Ed Grochowski

According to our database1, Ed Grochowski authored at least 10 papers between 1989 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2014
Improving the energy efficiency of Big Cores.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2012
Performance Benefits of Heterogeneous Computing in HPC Workloads.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2009
Larrabee: A Many-Core x86 Architecture for Visual Computing.
IEEE Micro, 2009

2008
Implications of device timing variability on full chip timing.
Proceedings of the 2008 International Symposium on Physical Design, 2008

2005
Mitigating Amdahl's Law through EPI Throttling.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
Best of Both Latency and Throughput.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Microarchitectural dI/dt Control.
IEEE Des. Test Comput., 2003

2002
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

1989
Issues in the implementation of the i486TM cache and bus.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989


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